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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
mb/emulation: Add SIMICS QSP support
SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register
besides DEVID/VENID. Likely because those are never used by an OS.
Not so good for firmware development.
ICH10 seems to be more properly implemented.
Working:
- Boots to EDK2
- TSEG works, ASEG is broken
- Graphics init works
Signed-off-by: Leon Gross <leon.gross(a)9elements.com>
Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36
---
M src/cpu/qemu-x86/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig.name
A src/mainboard/emulation/simics-qsp/Makefile.inc
A src/mainboard/emulation/simics-qsp/acpi.h
A src/mainboard/emulation/simics-qsp/acpi_tables.c
A src/mainboard/emulation/simics-qsp/board_info.txt
A src/mainboard/emulation/simics-qsp/bootblock.c
A src/mainboard/emulation/simics-qsp/cmos.default
A src/mainboard/emulation/simics-qsp/cmos.layout
A src/mainboard/emulation/simics-qsp/cpu.c
A src/mainboard/emulation/simics-qsp/devicetree.cb
A src/mainboard/emulation/simics-qsp/dsdt.asl
A src/mainboard/emulation/simics-qsp/exit_car.S
A src/mainboard/emulation/simics-qsp/hda_verb.c
A src/mainboard/emulation/simics-qsp/mainboard.c
A src/mainboard/emulation/simics-qsp/memmap.c
A src/mainboard/emulation/simics-qsp/memory.h
A src/mainboard/emulation/simics-qsp/northbridge.c
A src/mainboard/emulation/simics-qsp/romstage.c
A src/mainboard/emulation/simics-qsp/simics.h
A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd
A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd
M src/southbridge/intel/i82801jx/Kconfig
24 files changed, 1,249 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/11
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Change subject: soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
......................................................................
soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
This commit adds power limit settings for 4+8 28w SOC sku and renames
MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W
settings.
BUG=b:306677879
TEST=boot on rex with 4+8 SOC and power limit settings are correct
Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94
Signed-off-by: Curtis Chen <curtis.chen(a)intel.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/chipset.cb
2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/78796/2
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/emualtion: Add SIMICS QSP support
......................................................................
mb/emualtion: Add SIMICS QSP support
SIMICS QSP is weird, it doesn't implement a single X58 register
besides DEVID/VENID. Likely because those are never used by on OS.
Not so good for firmware development.
ICH10 seems to be more properly implemented.
Working:
- Boots to EDK2
- TSEG works, ASEG is broken
- Graphics init works
Signed-off-by: Leon Gross <leon.gross(a)9elements.com>
Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36
---
M src/cpu/qemu-x86/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig.name
A src/mainboard/emulation/simics-qsp/Makefile.inc
A src/mainboard/emulation/simics-qsp/acpi.h
A src/mainboard/emulation/simics-qsp/acpi_tables.c
A src/mainboard/emulation/simics-qsp/board_info.txt
A src/mainboard/emulation/simics-qsp/bootblock.c
A src/mainboard/emulation/simics-qsp/cmos.default
A src/mainboard/emulation/simics-qsp/cmos.layout
A src/mainboard/emulation/simics-qsp/cpu.c
A src/mainboard/emulation/simics-qsp/devicetree.cb
A src/mainboard/emulation/simics-qsp/dsdt.asl
A src/mainboard/emulation/simics-qsp/exit_car.S
A src/mainboard/emulation/simics-qsp/hda_verb.c
A src/mainboard/emulation/simics-qsp/mainboard.c
A src/mainboard/emulation/simics-qsp/memmap.c
A src/mainboard/emulation/simics-qsp/memory.h
A src/mainboard/emulation/simics-qsp/northbridge.c
A src/mainboard/emulation/simics-qsp/romstage.c
A src/mainboard/emulation/simics-qsp/simics.h
A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd
A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd
M src/southbridge/intel/i82801jx/Kconfig
24 files changed, 1,249 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/10
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 4:
(1 comment)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/78299/comment/1ce4c528_33771b6d :
PS3, Line 23: offers a range of laptops, PCs, HSM, and networking devices with coreboot and
: [Dasharo](https://dasharo.com/).
> no need for apologies ;) happily updating it to `HSMs`, new patchset incoming...
Done
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Change subject: mb/emualtion: Add SIMICS QSP support
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77905/comment/6c9d4a4e_82b7e8d6 :
PS9, Line 18: TSEG
Without a method supported by the northbridge/CPU to lock down this memory you just relocated SMM to a random region in memory and not TSEG. This is dangerous and considered improper. Find out how TSEG/ASEG works or skip SMM setup entirely.
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Change subject: drivers/intel/dptf: Add DCFG method support
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78386/comment/a386789d_5df65fad :
PS1, Line 9: that the OEM/ODM locks down
: thermal tuning beyond what is usually done on the given platform
Please elaborate. How is it locked down?
https://review.coreboot.org/c/coreboot/+/78386/comment/2c49dfae_91f13bb1 :
PS1, Line 9: After final production, it's possible that the OEM/ODM locks down
: thermal tuning beyond what is usually done on the given platform.
: In that case user space calibration tools should not try to adjust
: the thermal configuration of the system.
: By adding new DCFG (Device Configuration) method it allows the
: OEM/ODM to control this thermal tuning mechanism. It also gives
: the provision for user space to check the current mode.
: This method is based on BIOS specification document #640237.
Please add a blank line between paragraphs.
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Attention is currently required from: Julius Werner, Yu-Ping Wu.
Hello Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: arch/arm64/arch_timer: Fix possible overflow in multiplication
......................................................................
arch/arm64/arch_timer: Fix possible overflow in multiplication
The value from raw_read_cntfrq_el0() could be large enough to cause
overflow when multiplied by 1000000. To prevent this, both 1000000 and
tfreq can be reduced by dividing them by their GCD.
BUG=b:307790895
TEST=emerge-geralt coreboot
TEST=boot to kernel and check the timestamps from `cbmem`
Change-Id: I366667de05392913150414f0fa9058725be71c52
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/arch/arm64/arch_timer.c
1 file changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/78800/2
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