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Change subject: acpi: Move HPET generation to a common location
......................................................................
acpi: Move HPET generation to a common location
HPET is usually a feature of the hardware that needs no runtime to check
whether it is present or it is typically unconditionally
enabled. This means a simple Kconfig option to generate the ACPI tables
is sufficient, which allows reduction of boilerplate.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I38b9962a8d568267356256a3edc51348b9417e20
---
M src/acpi/Kconfig
M src/acpi/Makefile.inc
M src/acpi/acpi.c
M src/acpi/acpi_hpet.c
M src/include/acpi/acpi.h
M src/soc/amd/common/block/acpi/Kconfig
M src/soc/amd/common/block/acpi/Makefile.inc
D src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/include/amdblocks/acpi.h
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi.c
M src/soc/intel/broadwell/pch/Kconfig
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/acpi.c
M src/southbridge/amd/pi/hudson/Kconfig
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/Kconfig
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/lpc.c
37 files changed, 50 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/76128/8
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Change subject: Documentation: Make real time chats look less "official"
......................................................................
Abandoned
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Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
mb/emulation: Add SIMICS QSP support
SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register
besides DEVID/VENID. Likely because those are never used by an OS.
Not so good for firmware development.
ICH10 seems to be more properly implemented.
Working:
- Boots to EDK2
- TSEG works, ASEG is broken
- Graphics init works
Signed-off-by: Leon Gross <leon.gross(a)9elements.com>
Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36
---
M src/cpu/qemu-x86/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig.name
A src/mainboard/emulation/simics-qsp/Makefile.inc
A src/mainboard/emulation/simics-qsp/acpi.h
A src/mainboard/emulation/simics-qsp/acpi_tables.c
A src/mainboard/emulation/simics-qsp/board_info.txt
A src/mainboard/emulation/simics-qsp/bootblock.c
A src/mainboard/emulation/simics-qsp/cmos.default
A src/mainboard/emulation/simics-qsp/cmos.layout
A src/mainboard/emulation/simics-qsp/cpu.c
A src/mainboard/emulation/simics-qsp/devicetree.cb
A src/mainboard/emulation/simics-qsp/dsdt.asl
A src/mainboard/emulation/simics-qsp/exit_car.S
A src/mainboard/emulation/simics-qsp/hda_verb.c
A src/mainboard/emulation/simics-qsp/mainboard.c
A src/mainboard/emulation/simics-qsp/memmap.c
A src/mainboard/emulation/simics-qsp/memory.h
A src/mainboard/emulation/simics-qsp/northbridge.c
A src/mainboard/emulation/simics-qsp/romstage.c
A src/mainboard/emulation/simics-qsp/simics.h
A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd
A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd
M src/southbridge/intel/i82801jx/Kconfig
24 files changed, 1,249 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/13
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Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel: Support NO_SMM on modern SoCs
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/common/block/cpu/smmrelocate.c:
https://review.coreboot.org/c/coreboot/+/70377/comment/b60c8123_2c6e937b :
PS14, Line 217: *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
The codepath for this one is weird. It's a constant for a CPU.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
mb/emulation: Add SIMICS QSP support
SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register
besides DEVID/VENID. Likely because those are never used by an OS.
Not so good for firmware development.
ICH10 seems to be more properly implemented.
Working:
- Boots to EDK2
- TSEG works, ASEG is broken
- Graphics init works
Signed-off-by: Leon Gross <leon.gross(a)9elements.com>
Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36
---
M src/cpu/qemu-x86/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig.name
A src/mainboard/emulation/simics-qsp/Makefile.inc
A src/mainboard/emulation/simics-qsp/acpi.h
A src/mainboard/emulation/simics-qsp/acpi_tables.c
A src/mainboard/emulation/simics-qsp/board_info.txt
A src/mainboard/emulation/simics-qsp/bootblock.c
A src/mainboard/emulation/simics-qsp/cmos.default
A src/mainboard/emulation/simics-qsp/cmos.layout
A src/mainboard/emulation/simics-qsp/cpu.c
A src/mainboard/emulation/simics-qsp/devicetree.cb
A src/mainboard/emulation/simics-qsp/dsdt.asl
A src/mainboard/emulation/simics-qsp/exit_car.S
A src/mainboard/emulation/simics-qsp/hda_verb.c
A src/mainboard/emulation/simics-qsp/mainboard.c
A src/mainboard/emulation/simics-qsp/memmap.c
A src/mainboard/emulation/simics-qsp/memory.h
A src/mainboard/emulation/simics-qsp/northbridge.c
A src/mainboard/emulation/simics-qsp/romstage.c
A src/mainboard/emulation/simics-qsp/simics.h
A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd
A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd
M src/southbridge/intel/i82801jx/Kconfig
24 files changed, 1,249 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/12
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 4:
(1 comment)
File Documentation/distributions.md:
PS4:
Please restore the original order. Even if alphabetical order might make sense, that should be done in a separate patch.
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Change subject: cpu/x86: Support SMBASE relocation-only use-case
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> In this instance, we want to enable secure boot properly, which depends on the integrity of its vari […]
that explains why smmstore won't work for that. would it be possible to extend the smmstore to accomplish this?
another question i have is how the payload knows what soc or board dependent smi handler to add; not sure what the current status is in Intel, but on AMD we need a bit of smi handler code for entering s3/s4/s5
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/emulation/simics-qsp/memmap.c:
https://review.coreboot.org/c/coreboot/+/77905/comment/bb5303c5_de071cea :
PS4, Line 97: postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
: postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
> The simulator itself implements MTRR capabilities, why wouldn't we set them up properly? I think thi […]
Simulator is different with emulator. Simics actually simulates the RTL design.
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
Patch Set 11:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77905/comment/b91e7624_396758e8 :
PS9, Line 9: SIMICS QSP
> Quick Start Platfrom (QSP)
Done
https://review.coreboot.org/c/coreboot/+/77905/comment/f8a313f1_b0a163dc :
PS9, Line 20:
> Please paste the commands you use, and document the versions you tested with.
Can you specify what you mean with 'the commands you used' and which versions I should provide?
File src/mainboard/emulation/simics-qsp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/77905/comment/2e69c490_58477f4e :
PS4, Line 365: /****************************************************************
: * General purpose events
: ****************************************************************/
:
: Scope(\_GPE) {
: Name(_HID, "ACPI0006")
:
: Method(_L00) {
: }
: Method(_L01) {
: }
: Method(_L02) {
: }
: Method(_L03) {
: }
: Method(_L04) {
: }
: Method(_L05) {
: }
: Method(_L06) {
: }
: Method(_L07) {
: }
: Method(_L08) {
: }
: Method(_L09) {
: }
: Method(_L0A) {
: }
: Method(_L0B) {
: }
: Method(_L0C) {
: }
: Method(_L0D) {
: }
: Method(_L0E) {
: }
: Method(_L0F) {
: }
: }
> I'm not an expert on ACPI, but I thought in other
Done
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