coreboot-gerrit October 2023

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display
by Nick Vaccaro (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Paz Zcharya, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78691?usp=email ) Change subject: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Gerrit-Change-Number: 78691 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:41:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Paz Zcharya. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78691?usp=email ) Change subject: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > will get back with some more testing with USB-C display Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Gerrit-Change-Number: 78691 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Felix Singer (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78825?usp=email ) Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:08:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Felix Singer (Code Review) 31 Oct '23

31 Oct '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... soc/intel/cannonlake: Implement SoC sleep state array Adapted from Alderlake implementation, modified as needed. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/hatch (akemi). Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c 2 files changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 62462a8..ff93e2a 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -160,6 +160,76 @@ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } + +static struct min_sleep_state min_pci_sleep_states[] = { + { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_PEG0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_PEG1, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_PEG2, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TS, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UFS, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_ISH, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CNViWIFI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_SDCARD, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_EMMC, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE13, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE14, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE15, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE16, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE17, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE18, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE19, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE20, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE21, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE22, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE23, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE24, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_LPC, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_P2SB, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_TRACEHUB, ACPI_DEVICE_SLEEP_D3 }, +}; + +struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) +{ + *size = ARRAY_SIZE(min_pci_sleep_states); + return min_pci_sleep_states; +} + uint32_t soc_read_sci_irq_select(void) { return read32p(soc_read_pmc_base() + IRQ_REG); diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ece32c..7d40634 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -81,6 +81,7 @@ case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IGD: return "GFX0"; case PCH_DEVFN_ISH: return "ISHB"; + case SA_DEVFN_GNA: return "GNA"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_USBOTG: return "XDCI"; case PCH_DEVFN_THERMAL: return "THRM"; -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Paz Zcharya. Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Paz Zcharya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78691?usp=email to look at the new patch set (#4). Change subject: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display ...................................................................... soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display This patch fixes the redundent GFX modeset issue when a dual display is attached (e.g. an eDP display and an HDMI display). The issue was caused by the MBUS joining logic not considering the display type. This patch introduces three types of display: internal, external, and dual-display. The MBUS joining logic is then updated to consider the display type and ensure that the correct pipes are joined to the MBUS: For internal-only displays, only PIPE-A is joined to the MBUS. For external displays, no pipes are joined to the MBUS. For dual-displays, all available pipes are joined to the MBUS. BUG=b:284799726 TEST=Able to fix the redundent modeset issue when eDP and HDMI attached to the google/rex. Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 42 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/78691/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Gerrit-Change-Number: 78691 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Felix Singer (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:05:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/tigerlake: Implement SoC sleep state array
by Felix Singer (Code Review) 31 Oct '23

31 Oct '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78521?usp=email ) Change subject: soc/intel/tigerlake: Implement SoC sleep state array ...................................................................... soc/intel/tigerlake: Implement SoC sleep state array Copied from Alderlake implementation, modified as needed for Tigerlake. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/volteer (drobit). Change-Id: I34999891ea0d386328698109b6315d481de7c43a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.c 2 files changed, 68 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 9ff6e18..5c4c838 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -160,6 +160,65 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } +static struct min_sleep_state min_pci_sleep_states[] = { + { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_CPU_PCIE, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, +}; + +struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) +{ + *size = ARRAY_SIZE(min_pci_sleep_states); + return min_pci_sleep_states; +} + uint32_t soc_read_sci_irq_select(void) { return read32p(soc_read_pmc_base() + IRQ_REG); diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 024763d..dd24679 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -77,13 +77,18 @@ case SA_DEVFN_PEG1: return "PEG1"; case SA_DEVFN_PEG2: return "PEG2"; case SA_DEVFN_PEG3: return "PEG3"; + case SA_DEVFN_IGD: return "GFX0"; + case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; + case SA_DEVFN_TCSS_DMA0: return "TDM0"; + case SA_DEVFN_TCSS_DMA1: return "TDM1"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_IPU: return "IPU0"; case SA_DEVFN_GNA: return "GNA"; + case SA_DEVFN_DPTF: return "TCPU"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; @@ -125,9 +130,13 @@ case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_GSPI3: return "SPI3"; + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_GBE: return "GLAN"; + case PCH_DEVFN_SRAM: return "SRAM"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_CSE: return "HEC1"; } return NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/78521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34999891ea0d386328698109b6315d481de7c43a Gerrit-Change-Number: 78521 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/tigerlake: Implement SoC sleep state array
by Felix Singer (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78521?usp=email ) Change subject: soc/intel/tigerlake: Implement SoC sleep state array ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34999891ea0d386328698109b6315d481de7c43a Gerrit-Change-Number: 78521 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:02:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Paz Zcharya. Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Nick Vaccaro, Paz Zcharya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78691?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Paz Zcharya, Code-Review+2 by Eric Lai, Code-Review+2 by Nick Vaccaro, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display ...................................................................... soc/intel/cmn/gfx: Fix GFX modeset issue with dual-display This patch fixes the redundent GFX modeset issue when a dual display is attached (e.g. an eDP display and an HDMI display). The issue was caused by the MBUS joining logic not considering the display type. This patch introduces three types of display: internal, external, and dual-display. The MBUS joining logic is then updated to consider the display type and ensure that the correct pipes are joined to the MBUS: For internal-only displays, only PIPE-A is joined to the MBUS. For external displays, no pipes are joined to the MBUS. For dual-displays, all available pipes are joined to the MBUS. BUG=b:284799726 TEST=Able to fix the redundent modeset issue when eDP and HDMI attached to the google/rex. Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 43 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/78691/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Gerrit-Change-Number: 78691 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78825?usp=email ) Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:54:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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