coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, Werner Zeh. Hello Eric Lai, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78825?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... soc/intel/*: Correct ACPI device name for eMMC The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/alderlake/acpi/scs.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/elkhartlake/acpi/scs.asl M src/soc/intel/jasperlake/acpi/scs.asl 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/78825/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/amd/onyx: Include soc.asl file
by Felix Held (Code Review) 31 Oct '23

31 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78496?usp=email ) Change subject: mb/amd/onyx: Include soc.asl file ...................................................................... mb/amd/onyx: Include soc.asl file This patch includes the soc.asl from Genoa (SoC) folder, which in-turn includes pci_int_def.asl Change-Id: Id7a3b9c752546638f7b446510e17c44e9f10106d Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78496 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/onyx/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/onyx/dsdt.asl b/src/mainboard/amd/onyx/dsdt.asl index c7308a9..69b0e5e 100644 --- a/src/mainboard/amd/onyx/dsdt.asl +++ b/src/mainboard/amd/onyx/dsdt.asl @@ -12,4 +12,6 @@ ) { /* Start of ASL file */ #include <globalnvs.asl> + + #include <soc.asl> } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7a3b9c752546638f7b446510e17c44e9f10106d Gerrit-Change-Number: 78496 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Add PCI interrupt support
by Felix Held (Code Review) 31 Oct '23

31 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78392?usp=email ) Change subject: soc/amd/genoa: Add PCI interrupt support ...................................................................... soc/amd/genoa: Add PCI interrupt support This patch adds PCI interrupt details as per the Processor Programming Reference (PPR) version 0.25 (#55901), table 319. Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/amd/genoa/acpi/pci_int_defs.asl A src/soc/amd/genoa/acpi/soc.asl A src/soc/amd/genoa/include/soc/amd_pci_int_defs.h 3 files changed, 160 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/acpi/pci_int_defs.asl b/src/soc/amd/genoa/acpi/pci_int_defs.asl new file mode 100644 index 0000000..22455c5 --- /dev/null +++ b/src/soc/amd/genoa/acpi/pci_int_defs.asl @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} + +/* + * All PIC indexes are prefixed with P. + * All IO-APIC indexes are prefixed with I. + */ +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x10), + PSCI, 0x00000008, /* Index 0x10: SCI */ + PSB0, 0x00000008, /* Index 0x11: SMBUS0 */ + PASF, 0x00000008, /* Index 0x12: ASF */ + + Offset (0x16), + PPMN, 0x00000008, /* Index 0x16: PerMon */ + + Offset (0x1a), + PSIO, 0x00000008, /* Index 0x1A: SDIO */ + + Offset (0x50), + PGP0, 0x00000008, /* Index 0x50: GPP0 */ + PGP1, 0x00000008, /* Index 0x51: GPP1 */ + PGP2, 0x00000008, /* Index 0x52: GPP2 */ + PGP3, 0x00000008, /* Index 0x53: GPP3 */ + + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0/I3C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1/I3C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2/I3C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3/I3C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0x90), + ISCI, 0x00000008, /* Index 0x90: SCI */ + ISB0, 0x00000008, /* Index 0x91: SMBUS0 */ + IASF, 0x00000008, /* Index 0x92: ASF */ + + Offset (0x96), + IPMN, 0x00000008, /* Index 0x96: PerMon */ + + Offset (0x9a), + ISIO, 0x00000008, /* Index 0x9A: SDIO */ + + Offset (0xD0), + IGP0, 0x00000008, /* Index 0xD0: GPP0 */ + IGP1, 0x00000008, /* Index 0xD1: GPP1 */ + IGP2, 0x00000008, /* Index 0xD2: GPP2 */ + IGP3, 0x00000008, /* Index 0xD3: GPP3 */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0/I3C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1/I3C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2/I3C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3/I3C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl new file mode 100644 index 0000000..88b0df8 --- /dev/null +++ b/src/soc/amd/genoa/acpi/soc.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include "pci_int_defs.asl" +} /* End \_SB scope */ diff --git a/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h b/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h new file mode 100644 index 0000000..7d2bb39 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_AMD_PCI_INT_DEFS_H +#define AMD_GENOA_AMD_PCI_INT_DEFS_H + +/* + * * PIRQ and device routing - these define the index into the + * * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + * */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_HPET_L 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_HPET_H 0x0b /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS0 */ +#define PIRQ_ASF 0x12 /* ASF */ +/* 0x13-0x15 reserved */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +/* 0x17-0x19 reserved */ +#define PIRQ_SDIO 0x1a /* SDIO */ +/* 0x1b-0x49 reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x59 reserved */ +#define PIRQ_SCI 0x60 /* SCI Interrupt */ +#define PIRQ_SMI 0x61 /* SMI Interrupt */ +#define PIRQ_GPIO 0x62 /* GPIO Interrupt */ +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0/I3C0 */ +#define PIRQ_I2C1 0x71 /* I2C1/I3C1 */ +#define PIRQ_I2C2 0x72 /* I2C2/I3C2 */ +#define PIRQ_I2C3 0x73 /* I2C3/I3C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_I2C5 0x77 /* I2C5 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ + +#endif /* AMD_GENOA_AMD_PCI_INT_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336 Gerrit-Change-Number: 78392 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Paul Menzel (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77905/comment/399cc678_a3692e38 : PS9, Line 20: > Can you specify what you mean with 'the commands you used' and which versions I should provide? You write “Boots to EDK2”. How can I reproduce that? -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:21:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Leon Groß <leon.gross(a)9elements.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (1 comment) File src/mainboard/emulation/simics-qsp/northbridge.c: https://review.coreboot.org/c/coreboot/+/77905/comment/0dab3f25_b86ca7d8 : PS4, Line 218: tatic void northbridge_enable(struct device *dev) : { : /* Set the operations if it is a special bus type */ : if (dev->path.type == DEVICE_PATH_DOMAIN) { : dev->ops = &pci_domain_ops; : } : else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { : dev->ops = &cpu_bus_ops; : } : } > Do you mean putting something in the device tree like `device cpu_cluster 0 on ops cpu_bus_ops end` and then the same for the the domain or am I misunderstanding? yes -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Leon Groß <leon.gross(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, Werner Zeh. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78825?usp=email ) Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:09:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Martin L Roth, Nick Vaccaro, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/78522/comment/790ddd90_2fe82c24 : PS1, Line 130: case PCH_DEVFN_EMMC: return "PEMC"; > nice catch LoL Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:09:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Werner Zeh. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78825?usp=email ) Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... soc/intel/*: Correct ACPI device name for eMMC The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/alderlake/acpi/scs.asl M src/soc/intel/braswell/acpi/scc.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/elkhartlake/acpi/scs.asl M src/soc/intel/jasperlake/acpi/scs.asl 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/78825/1 diff --git a/src/soc/intel/alderlake/acpi/scs.asl b/src/soc/intel/alderlake/acpi/scs.asl index aac78e8..d39c66d 100644 --- a/src/soc/intel/alderlake/acpi/scs.asl +++ b/src/soc/intel/alderlake/acpi/scs.asl @@ -18,7 +18,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name(TEMP, 0) diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 5efe5a0..469e7d2 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -63,7 +63,7 @@ } } -Device (PEMC) +Device (EMMC) { Name (_ADR, 0x00100000) diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 7def761..fcadcbd 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) diff --git a/src/soc/intel/elkhartlake/acpi/scs.asl b/src/soc/intel/elkhartlake/acpi/scs.asl index c6d71c1..3955402 100644 --- a/src/soc/intel/elkhartlake/acpi/scs.asl +++ b/src/soc/intel/elkhartlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index b58608f..491df51 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Martin L Roth, Matt DeVillier, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Martin L Roth, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78522?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... soc/intel/cannonlake: Implement SoC sleep state array Adapted from Alderlake implementation, modified as needed. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/hatch (akemi). Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c 2 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/78522/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023