coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: Use common GCD function
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner, Yidi Lin, Yu-Ping Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78799?usp=email ) Change subject: Use common GCD function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Gerrit-Change-Number: 78799 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 16:12:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: lib: Add GCD function
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner, Yidi Lin, Yu-Ping Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78798?usp=email ) Change subject: lib: Add GCD function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Gerrit-Change-Number: 78798 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 16:12:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: [RFC] drivers/option: Add forms in cbtables
by Patrick Rudolph (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Lean Sheng Tan, Maximilian Brune, Nico Huber, Sean Rhodes. Patrick Rudolph has uploaded a new patch set (#18) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [RFC] drivers/option: Add forms in cbtables ...................................................................... [RFC] drivers/option: Add forms in cbtables Introduce a mechanism so that coreboot can provide a list of options to post-coreboot code. The options are grouped together into forms and have a meaning name and optional help text. This can be used to let payloads know which options should be displayed in a setup menu, for instance. Although this system was written to be used with edk2, it has been designed with flexibility in mind so that other payloads can also make use of this mechanism. The system currently lacks a way to describe where to find option values. This information is stored in a set of data structures specifically created for this purpose. This format is known as CFR, which means "coreboot forms representation" or "cursed forms representation". Although the "forms representation" is borrowed from UEFI, CFR can be used in non-UEFI scenarios as well. The data structures are implemented as an extension of cbtables records to support nesting. It should not break backwards compatibility because the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children records. The concept of record nesting is borrowed from the records for CMOS options. It is not possible to reuse the CMOS records because they are too closely coupled with CMOS options; using these structures would needlessly restrict more capable backends to what can be done with CMOS options, which is undesired. Because CFR supports variable-length components, directly transforming options into CFR structures is not a trivial process. Furthermore, CFR structures need to be written in one go. Because of this, abstractions exist to generate CFR structures from a set of "setup menu" structures that are coreboot-specific and could be integrated with the devicetree at some point. Note that `struct sm_object` is a tagged union. This is used to have lists of options in an array, as building linked lists of options at runtime is extremely impractical because options would have to be added at the end of the linked list to maintain option order. To avoid mistakes defining `struct sm_object` values, helper macros exist for supported option types. The macros also provide some type checking as they initialise specific union members. It should be possible to extend CFR support for more sophisticated options like fan curve points. Feedback about this is highly appreciated. Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/drivers/cfr_internal.md M Documentation/drivers/index.md A src/drivers/option/Kconfig A src/drivers/option/Makefile.inc A src/drivers/option/cfr.c A src/drivers/option/cfr.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/lib/program.ld 9 files changed, 603 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74121/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 18 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains
by Patrick Rudolph (Code Review) 31 Oct '23

31 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78829?usp=email ) Change subject: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains ...................................................................... sb/intel/bd82x6x/early_usb: Add USB TX/RX gains Describe the USB 'current' settings based on MRC.bin that converts the USB trace length to a predefined register value. MRC.bin decides which setting to use based on the PC type, mobile or desktop, and the trace length. Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78829/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 27a9c57..1d574e1 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -15,9 +15,9 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, - 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, - 0x20000353 }; + const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, + USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, + USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 }; int i; /* Unlock registers. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 6d164ea..656b641 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -380,6 +380,18 @@ #define USBIR12 0x3530 /* 32bit */ #define USBIR13 0x3534 /* 32bit */ +/* Up to 5" onboard trace length */ +#define USBIR_TXRX_GAIN_MOBILE_LOW 0x20000153 + +/* Up to 6" onboard trace length */ +#define USBIR_TXRX_GAIN_DESKTOP_LOW 0x20000F53 + +/* Up to 14" onboard trace length, up to 8" on wires */ +#define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 + +/* Up to 10" onboard trace length, up to 15" on wires */ +#define USBIR_TXRX_GAIN_HIGH 0x2000055B + /* Miscellaneous Control Register */ #define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Gerrit-Change-Number: 78829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/autoport: Improve USB code
by Patrick Rudolph (Code Review) 31 Oct '23

31 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78828?usp=email ) Change subject: util/autoport: Improve USB code ...................................................................... util/autoport: Improve USB code Currently autoport fills in USB current '0' if the detected settings isn't one of the known settings. This works as 0 is a valid setting from C point of view, but it's not supported on desktop PCs and on mobile platform results in the lowest possible USB PHY gain. Thus this might cause instabilities as the original firmware had stronger USB drive currents and gain settings. Add more known USB current fields to the map and generate a FIXME as comment when the detected current isn't one of the known entries instead of defaulting to 0. Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/autoport/bd82x6x.go 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78828/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 6ce15a2..85db8be 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -309,6 +309,10 @@ 0x2000055b: 2, 0x20000f51: 3, 0x2000094a: 4, + 0x2000035f: 5, + 0x20000f53: 6, + 0x20000357: 7, + 0x20000353: 8, } for port := uint(0); port < 14; port++ { @@ -327,10 +331,16 @@ } } } - fmt.Fprintf(sb, "\t{ %d, %d, %d },\n", + current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] + comment := "" + if !ok { + comment = "// FIXME: Unknown current" + } + fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n", ((inteltool.RCBA[0x359c]>>port)&1)^1, - currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], - OCPin) + current, + OCPin, + comment) } sb.WriteString("};\n") -- To view, visit https://review.coreboot.org/c/coreboot/+/78828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Gerrit-Change-Number: 78828 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting
by Patrick Rudolph (Code Review) 31 Oct '23

31 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78827?usp=email ) Change subject: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting ...................................................................... sb/intel/bd82x6x/early_usb: Print error for invalid USB setting According to BWG the USB current setting 0 should not be used for desktop boards. As autoport defaults to 0 if the USB current doesn't match one of the lookup table entries most of the desktop boards in tree have a such setting. Print an error to alert users of such boards to update the USB current settings. Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78827/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 654d44b..27a9c57 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -23,8 +23,15 @@ /* Unlock registers. */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); - for (i = 0; i < 14; i++) + for (i = 0; i < 14; i++) { + if (get_platform_type() == PLATFORM_DESKTOP_SERVER && + portmap[i].current == 0) { + printk(BIOS_ERR, "%s: USB%02d: current setting of 0 is not a valid setting for desktop!\n", + __func__, i); + } + RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; + } for (i = 0; i < 10; i++) RCBA32(0x3538 + 4 * i) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/78827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Gerrit-Change-Number: 78827 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge: Use SA devid to identify PC type
by Patrick Rudolph (Code Review) 31 Oct '23

31 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78826?usp=email ) Change subject: nb/intel/sandybridge: Use SA devid to identify PC type ...................................................................... nb/intel/sandybridge: Use SA devid to identify PC type Instead or using MSR IA32_PLATFORM_ID read the SystemAgent device id to figure out the PC type. This follows the BWG which suggest to not use MSR IA32_PLATFORM_ID for system identification. Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/Makefile.inc D src/cpu/intel/model_206ax/common.c M src/northbridge/intel/sandybridge/common.c 3 files changed, 9 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78826/1 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index cd947df..e6e6e37 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -9,10 +9,6 @@ ramstage-y += acpi.c -ramstage-y += common.c -romstage-y += common.c -smm-y += common.c - smm-y += finalize.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c deleted file mode 100644 index a881314..0000000 --- a/src/cpu/intel/model_206ax/common.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include "model_206ax.h" - -int get_platform_id(void) -{ - msr_t msr; - - msr = rdmsr(IA32_PLATFORM_ID); - /* Read Platform Id Bits 52:50 */ - return (msr.hi >> 18) & 0x7; -} diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index a8f718c..9625f6b 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -2,14 +2,18 @@ #include <console/console.h> #include <device/device.h> -#include <cpu/intel/model_206ax/model_206ax.h> #include "sandybridge.h" enum platform_type get_platform_type(void) { - const int id = get_platform_id(); - if (id != 1 && id != 4) - printk(BIOS_WARNING, "Unknown platform id 0x%x\n", id); + struct device *dev = pcidev_on_root(0, 0); - return (id == 4) ? PLATFORM_MOBILE : PLATFORM_DESKTOP_SERVER; + switch (pci_read_config16(dev, PCI_DEVICE_ID) & 0xc) { + case 0x0: /* Desktop */ + return PLATFORM_DESKTOP_SERVER; + case 0x4: /* Mobile */ + return PLATFORM_MOBILE; + case 0x8: /* Server */ + return PLATFORM_DESKTOP_SERVER; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/78826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Gerrit-Change-Number: 78826 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Lean Sheng Tan (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Leon Groß, Nico Huber, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (1 comment) Patchset: PS4: > I also wonder, what's the use case for this? i mean it is no harm to add more support to the platform for coreboot i guess? It is a nice addition as well. As it does have specific use cases (although quite limited): as Intel or silicon vendors usually use Simics for the RTL simulation before the actual silicon is available, actively used by the internal engineers for that. EDK2 and Slimbootloader already have nice support for Simics: https://slimbootloader.github.io/supported-hardware/qsp.html https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/Simi… -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 16:00:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/genoa: Add openSIL to Genoa Kconfig
by Martin L Roth (Code Review) 31 Oct '23

31 Oct '23

Martin L Roth has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/78635?usp=email ) Change subject: soc/amd/genoa: Add openSIL to Genoa Kconfig ...................................................................... soc/amd/genoa: Add openSIL to Genoa Kconfig Select opensil & opensil_genoa. This enables openSIL for Genoa, allowing the build to be tested. Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/soc/amd/genoa/Kconfig M src/vendorcode/amd/opensil/Makefile.inc 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/78635/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2 Gerrit-Change-Number: 78635 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Nico Huber (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (1 comment) Patchset: PS4: > I don't see any benefit of having support for SIMICS default QSP target as it's emulating even less […] I also wonder, what's the use case for this? -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 15:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2023