coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/78522/comment/0644ccb4_ca8e7e3b : PS1, Line 130: case PCH_DEVFN_EMMC: return "PEMC"; > this comment made me check and realize that there's a mismatch for other intel SoCs as well, so I'll […] nice catch LoL -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Leon Groß (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, Paul Menzel. Leon Groß has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (5 comments) File src/mainboard/emulation/simics-qsp/Kconfig: https://review.coreboot.org/c/coreboot/+/77905/comment/4876a82d_ed6c1ad8 : PS4, Line 112: 128 > 1 as the supported CPU count isn't passed from emulator to guest like it's done on qemu. […] Done File src/mainboard/emulation/simics-qsp/dsdt.asl: https://review.coreboot.org/c/coreboot/+/77905/comment/830a62dc_0ec33eb6 : PS4, Line 365: /**************************************************************** : * General purpose events : ****************************************************************/ : : Scope(\_GPE) { : Name(_HID, "ACPI0006") : : Method(_L00) { : } : Method(_L01) { : } : Method(_L02) { : } : Method(_L03) { : } : Method(_L04) { : } : Method(_L05) { : } : Method(_L06) { : } : Method(_L07) { : } : Method(_L08) { : } : Method(_L09) { : } : Method(_L0A) { : } : Method(_L0B) { : } : Method(_L0C) { : } : Method(_L0D) { : } : Method(_L0E) { : } : Method(_L0F) { : } : } > remove? Done File src/mainboard/emulation/simics-qsp/gpio.c: https://review.coreboot.org/c/coreboot/+/77905/comment/bdd442ba_d1f0907a : PS4, Line 87: mainboard_gpio_map > No, I think we can remove this. Correction: Since the init function of the southbridge relies on that, we should maybe mock it instead of removing it entirely / creating a new south bridge init that does not rely on this. File src/mainboard/emulation/simics-qsp/memmap.c: https://review.coreboot.org/c/coreboot/+/77905/comment/21c00699_82032ed0 : PS4, Line 39: uint32_t make_pciexbar(void) > Yes, we can remove this as well as the encoding and the defintion in the header. Done File src/mainboard/emulation/simics-qsp/northbridge.c: https://review.coreboot.org/c/coreboot/+/77905/comment/8ea9899a_8cc8dada : PS4, Line 218: tatic void northbridge_enable(struct device *dev) : { : /* Set the operations if it is a special bus type */ : if (dev->path.type == DEVICE_PATH_DOMAIN) { : dev->ops = &pci_domain_ops; : } : else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { : dev->ops = &cpu_bus_ops; : } : } > Set these with ops in devicetree rather than at runtime. Do you mean putting something in the device tree like `device cpu_cluster 0 on ops cpu_bus_ops end` and then the same for the the domain or am I misunderstanding? -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:01:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Leon Groß <leon.gross(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: sb/intel/lynxpoint: Don't generate second SSDT
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Felix Singer. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76129?usp=email to look at the new patch set (#10). Change subject: sb/intel/lynxpoint: Don't generate second SSDT ...................................................................... sb/intel/lynxpoint: Don't generate second SSDT Move the entries in SSDT to acpi_fill_ssdt(). There is no need for a separate table. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e --- M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 16 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/76129/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/76129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e Gerrit-Change-Number: 76129 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: sb/intel/lynxpoint: Don't generate second SSDT
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Felix Singer. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76129?usp=email ) Change subject: sb/intel/lynxpoint: Don't generate second SSDT ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76129/comment/0af964a9_697acac6 : PS7, Line 9: is need > missing word: **no** need Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e Gerrit-Change-Number: 76129 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Tue, 31 Oct 2023 14:00:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: acpi: Move HPET generation to a common location
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Cliff Huang, Felix Singer, Fred Reitberger, Jason Glenesk, Jeff Daly, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak, Vanessa Eusebio. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76128?usp=email ) Change subject: acpi: Move HPET generation to a common location ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76128/comment/f6854c6c_4442a63a : PS6, Line 9: to > that "to" sounds not right here. Done https://review.coreboot.org/c/coreboot/+/76128/comment/46235f06_567b276e : PS6, Line 12: suffices > typo: sufficient? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38b9962a8d568267356256a3edc51348b9417e20 Gerrit-Change-Number: 76128 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/78522/comment/3e2eb6be_0156275c : PS1, Line 130: case PCH_DEVFN_EMMC: return "PEMC"; > to match the actual ACPI device name in `src/soc/intel/cannonlake/acpi/scs.asl. […] this comment made me check and realize that there's a mismatch for other intel SoCs as well, so I'll remove the change here and fix them all in one patch -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/78522/comment/f0186e30_d3d543b0 : PS1, Line 130: case PCH_DEVFN_EMMC: return "PEMC"; > to match the actual ACPI device name in `src/soc/intel/cannonlake/acpi/scs.asl. […] I think change the name in src/soc/intel/cannonlake/acpi/scs.asl is more make sense. thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:58:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/tigerlake: Implement SoC sleep state array
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78521?usp=email ) Change subject: soc/intel/tigerlake: Implement SoC sleep state array ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78521/comment/e15f76fb_92ba5ba8 : PS1, Line 9: Alderlake > Alder Lake […] Done https://review.coreboot.org/c/coreboot/+/78521/comment/7d898bd2_801547fd : PS1, Line 12: TEST=build/boot Win11, Linux on google/volteer (drobit). > Currently, Linux only uses the LPI constraint list for debugging purposes, but there is a patch on t […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34999891ea0d386328698109b6315d481de7c43a Gerrit-Change-Number: 78521 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cannonlake: Implement SoC sleep state array
by Matt DeVillier (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78522?usp=email ) Change subject: soc/intel/cannonlake: Implement SoC sleep state array ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/78522/comment/f70befbc_89791b7a : PS1, Line 130: case PCH_DEVFN_EMMC: return "PEMC"; > why change this name? to match the actual ACPI device name in `src/soc/intel/cannonlake/acpi/scs.asl.` I could change that one to `EMMC` if it makes more sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/78522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Gerrit-Change-Number: 78522 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:54:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Arthur Heymans (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77905?usp=email ) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... Patch Set 13: (1 comment) File src/mainboard/emulation/simics-qsp/memmap.c: https://review.coreboot.org/c/coreboot/+/77905/comment/7045e87c_b9e90565 : PS4, Line 97: postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); : postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); > Simulator is different with emulator. Simics actually simulates the RTL design. I'm confused. Most of the real hardware is not there, however MTRR are? Also you're not setting up MTRR properly, which you need to do in ramstage during CPU init. You just set up a WB cached frame to use after romstage. Either do it completely right or drop this. -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 13 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 13:53:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Leon Groß <leon.gross(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2023