coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: mb/emualtion: Add SIMICS QSP support
by Leon Groß (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph. Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77905?usp=email to look at the new patch set (#6). Change subject: mb/emualtion: Add SIMICS QSP support ...................................................................... mb/emualtion: Add SIMICS QSP support SIMICS QSP is weird, it doesn't implement a single X58 register besides DEVID/VENID. Likely because those are never used by on OS. Not so good for firmware development. ICH10 seems to be more properly implemented. Working: - Boots to EDK2 - TSEG works, ASEG is broken - Graphics init works Signed-off-by: Leon Gross <leon.gross(a)9elements.com> Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 --- M src/cpu/qemu-x86/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig.name A src/mainboard/emulation/simics-qsp/Makefile.inc A src/mainboard/emulation/simics-qsp/acpi.h A src/mainboard/emulation/simics-qsp/acpi_tables.c A src/mainboard/emulation/simics-qsp/board_info.txt A src/mainboard/emulation/simics-qsp/bootblock.c A src/mainboard/emulation/simics-qsp/cmos.default A src/mainboard/emulation/simics-qsp/cmos.layout A src/mainboard/emulation/simics-qsp/cpu.c A src/mainboard/emulation/simics-qsp/devicetree.cb A src/mainboard/emulation/simics-qsp/dsdt.asl A src/mainboard/emulation/simics-qsp/exit_car.S A src/mainboard/emulation/simics-qsp/gpio.c A src/mainboard/emulation/simics-qsp/hda_verb.c A src/mainboard/emulation/simics-qsp/mainboard.c A src/mainboard/emulation/simics-qsp/memmap.c A src/mainboard/emulation/simics-qsp/memory.h A src/mainboard/emulation/simics-qsp/northbridge.c A src/mainboard/emulation/simics-qsp/romstage.c A src/mainboard/emulation/simics-qsp/simics.h A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd M src/southbridge/intel/i82801jx/Kconfig 25 files changed, 1,433 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 6 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/emualtion: Add SIMICS QSP support
by Leon Groß (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Angel Pons, Benjamin Doron, Christian Walter, Lean Sheng Tan, Leon Groß, Patrick Rudolph. Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77905?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review-1 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: mb/emualtion: Add SIMICS QSP support ...................................................................... mb/emualtion: Add SIMICS QSP support SIMICS QSP is weird, it doesn't implement a single X58 register besides DEVID/VENID. Likely because those are never used by on OS. Not so good for firmware development. ICH10 seems to be more properly implemented. Working: - Boots to EDK2 - TSEG works, ASEG is broken - Graphics init works Signed-off-by: Leon Gross <leon.gross(a)9elements.com> Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 --- M src/cpu/qemu-x86/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig.name A src/mainboard/emulation/simics-qsp/Makefile.inc A src/mainboard/emulation/simics-qsp/acpi.h A src/mainboard/emulation/simics-qsp/acpi_tables.c A src/mainboard/emulation/simics-qsp/board_info.txt A src/mainboard/emulation/simics-qsp/bootblock.c A src/mainboard/emulation/simics-qsp/cmos.default A src/mainboard/emulation/simics-qsp/cmos.layout A src/mainboard/emulation/simics-qsp/cpu.c A src/mainboard/emulation/simics-qsp/devicetree.cb A src/mainboard/emulation/simics-qsp/dsdt.asl A src/mainboard/emulation/simics-qsp/exit_car.S A src/mainboard/emulation/simics-qsp/gpio.c A src/mainboard/emulation/simics-qsp/hda_verb.c A src/mainboard/emulation/simics-qsp/mainboard.c A src/mainboard/emulation/simics-qsp/memmap.c A src/mainboard/emulation/simics-qsp/memory.h A src/mainboard/emulation/simics-qsp/northbridge.c A src/mainboard/emulation/simics-qsp/romstage.c A src/mainboard/emulation/simics-qsp/simics.h A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd M src/southbridge/intel/i82801jx/Kconfig 25 files changed, 1,436 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 5 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Sumeet R Pawnikar (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Kapil Porwal, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78386/comment/2ac7ffbe_2fca81d1 : PS1, Line 13: DCFG (Device Configuration) method > can you point me at the usage of DCFG or some spec? Please refer BIOS specification document #640237 and we have validated this as mentioned in TEST information. -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 09:34:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Kapil Porwal, Sumeet R Pawnikar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78386/comment/9282107c_0961a6e8 : PS1, Line 13: DCFG (Device Configuration) method can you point me at the usage of DCFG or some spec? -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 09:19:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Sumeet R Pawnikar (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Kapil Porwal, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please, help to review with +2 to get this merge. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 09:16:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI
by Yidi Lin (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78824?usp=email ) Change subject: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Gerrit-Change-Number: 78824 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 09:13:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI
by Yu-Ping Wu (Code Review) 31 Oct '23

31 Oct '23

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78824?usp=email ) Change subject: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI ...................................................................... mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI Enable FW_CONFIG for geralt so that the information can be passed to payloads via coreboot tables. BUG=b:157692450 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/geralt/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/78824/1 diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index 54c51d8..6817143 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -35,6 +35,8 @@ select HAVE_LINEAR_FRAMEBUFFER select RTC select MIPI_PANEL_BOE_TV110C9M_LL0 if BOARD_GOOGLE_GERALT + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/78824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Gerrit-Change-Number: 78824 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/cmn/block/cse: Support sending EOP from payload
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner, Kapil Porwal, Lean Sheng Tan, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74765?usp=email ) Change subject: soc/intel/cmn/block/cse: Support sending EOP from payload ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: > let me test this patch there is 10ms boot regression -- To view, visit https://review.coreboot.org/c/coreboot/+/74765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523 Gerrit-Change-Number: 74765 Gerrit-PatchSet: 12 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 08:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/quandiso: Add VBT data file
by Robert Chen (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel, Subrata Banik. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77588?usp=email ) Change subject: mb/google/brya/var/quandiso: Add VBT data file ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77588/comment/d2c302d6_84ee933f : PS6, Line 10: The VBT file is copied from : chromeos internal source and based on yaviks VBT. > It’d be great if you also documented, in what ways it was changed. Quandiso have the same vbt setting with yaviks, so it is exactly the same with yaviks PVT phase file. -- To view, visit https://review.coreboot.org/c/coreboot/+/77588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4 Gerrit-Change-Number: 77588 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 08:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mtlrvp: add EC_SI region in flash map
by Deepti Deshatty (Code Review) 31 Oct '23

31 Oct '23

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78797?usp=email ) Change subject: mtlrvp: add EC_SI region in flash map ...................................................................... mtlrvp: add EC_SI region in flash map Change-Id: I03c368da0614f7da2a8e433b27bc65dcbbd8612f --- M src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/78797/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index f225aa5..9bbad64 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -74,7 +74,8 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_shared_flash_ec_ap.fmd" if BOARD_INTEL_MTLRVP_P_MCHP + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC config MAINBOARD_FAMILY string diff --git a/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd new file mode 100644 index 0000000..d49ac0c7 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd @@ -0,0 +1,56 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_EC 512K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 4400K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 4400K + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 3M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78797?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c368da0614f7da2a8e433b27bc65dcbbd8612f Gerrit-Change-Number: 78797 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2023