coreboot-gerrit October 2023

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[M] Change in coreboot[master]: mtlrvp: add EC_SI region in flash map
by Deepti Deshatty (Code Review) 31 Oct '23

31 Oct '23

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78797?usp=email ) Change subject: mtlrvp: add EC_SI region in flash map ...................................................................... mtlrvp: add EC_SI region in flash map Change-Id: I03c368da0614f7da2a8e433b27bc65dcbbd8612f --- M src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/78797/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index f225aa5..9bbad64 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -74,7 +74,8 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_shared_flash_ec_ap.fmd" if BOARD_INTEL_MTLRVP_P_MCHP + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC config MAINBOARD_FAMILY string diff --git a/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd new file mode 100644 index 0000000..d49ac0c7 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd @@ -0,0 +1,56 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_EC 512K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 4400K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 4400K + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 3M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78797?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c368da0614f7da2a8e433b27bc65dcbbd8612f Gerrit-Change-Number: 78797 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Curtis Chen, Eran Mitrani, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78796?usp=email ) Change subject: soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Gerrit-Change-Number: 78796 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 08:24:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
by Curtis Chen (Code Review) 31 Oct '23

31 Oct '23

Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78796?usp=email ) Change subject: soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU ...................................................................... soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU This commit adds power limit settings for 4+8 15w SOC sku and renames MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W settings. BUG=b:306677879 TEST=boot on rex with 4+8 SOC and power limit settings are correct Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/78796/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 57471b7..e860ba97 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -43,7 +43,7 @@ /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { MTL_P_282_242_CORE, - MTL_P_682_CORE, + MTL_P_682_482_CORE, MTL_POWER_LIMITS_COUNT }; @@ -61,7 +61,8 @@ } cpuid_to_mtl[] = { { PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, - { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_CORE, TDP_28W }, + { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, }; /* Types of display ports */ diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 4a49f22..69d0df3 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -8,7 +8,7 @@ .tdp_pl4 = 114, }" - register "power_limits_config[MTL_P_682_CORE]" = "{ + register "power_limits_config[MTL_P_682_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 120, -- To view, visit https://review.coreboot.org/c/coreboot/+/78796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Gerrit-Change-Number: 78796 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Fabian Groffen (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Felix Singer, Keith Hui, Patrick Rudolph. Fabian Groffen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77046?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... Patch Set 7: (1 comment) File 3rdparty/amd_blobs: PS6: > I guess this is not intended oops, no. -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 7 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 08:01:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Fabian Groffen (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Fabian Groffen, Keith Hui, Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77046?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H This board is based off ga-b75m-d3h, which uses the same SuperIO chip. It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with 2 SATA3 ports next to the 4 SATA2 ports. Flashing notes: These boards come with dual-BIOS feature. This is set of two unremovable what appears to be identical chips marked M_BIOS and B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have a payload and setup ready to boot a Linux system with iomem=relaxed or similar. Immediately use flashrom -p internal to flash the same firmware again. If you skip this step your next boot will show weird exception traces in either coreboot or your payload. Flashing from there via the chip is very difficult (you have to try many times in order to get a booting run), which can all be remedied by doing a flash from internal. I suppose the dual-BIOS feature is somewhat in the way here. Tested with: - CPU Core i7-3770S - RAM single bank 4GB CL11, two banks 4+4GB CL11 - OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload - Intel ME stripped - Integrated graphics with libgfxinit - (boot from) SATA2, SATA3 ports - Rear and mainboard connector USB ports, supporting boot - Atheros GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS events) - S3 suspend/resume - PWM FAN control, FAN speed readings - Temperature sensor readings Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab --- A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h 21 files changed, 681 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/77046/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 7 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vboot: Add catchall recovery reason for unspecified phase 4 errors
by Yu-Ping Wu (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78821?usp=email ) Change subject: vboot: Add catchall recovery reason for unspecified phase 4 errors ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If00f8f8a5d17aa113e0325aad58d367f244aca49 Gerrit-Change-Number: 78821 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 07:34:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Yu-Ping Wu (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78820?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8 Gerrit-Change-Number: 78820 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 07:34:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config
by Rex Chou (Code Review) 31 Oct '23

31 Oct '23

Rex Chou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78795?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/78795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Gerrit-Change-Number: 78795 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config
by Rex Chou (Code Review) 31 Oct '23

31 Oct '23

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78843?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config ...................................................................... mb/google/nissa/var/craaskov: Disable storage devices based on fw_config Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/Makefile.inc A src/mainboard/google/brya/variants/craaskov/fw_config.c M src/mainboard/google/brya/variants/craaskov/overridetree.cb M src/mainboard/google/brya/variants/craaskov/variant.c 4 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/78843/1 diff --git a/src/mainboard/google/brya/variants/craaskov/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/Makefile.inc index f3987ab..7250b58 100644 --- a/src/mainboard/google/brya/variants/craaskov/Makefile.inc +++ b/src/mainboard/google/brya/variants/craaskov/Makefile.inc @@ -2,4 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c -ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/craaskov/fw_config.c b/src/mainboard/google/brya/variants/craaskov/fw_config.c new file mode 100644 index 0000000..800fc1f --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/fw_config.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 9cac704..8c29567 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -195,6 +195,14 @@ end end device ref pcie_rp7 off end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/craaskov/variant.c b/src/mainboard/google/brya/variants/craaskov/variant.c index 6a79780..68f128c 100644 --- a/src/mainboard/google/brya/variants/craaskov/variant.c +++ b/src/mainboard/google/brya/variants/craaskov/variant.c @@ -1,8 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <device/device.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; } + +void variant_devtree_update(void) +{ + struct device *emmc = DEV_PTR(emmc); + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + + if (!fw_config_is_provisioned()) { + printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "eMMC disabled by fw_config\n"); + emmc->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Gerrit-Change-Number: 78843 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config
by Rex Chou (Code Review) 31 Oct '23

31 Oct '23

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78795?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config ...................................................................... mb/google/nissa/var/craaskov: Disable storage devices based on fw_config Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/Makefile.inc A src/mainboard/google/brya/variants/craaskov/fw_config.c M src/mainboard/google/brya/variants/craaskov/overridetree.cb M src/mainboard/google/brya/variants/craaskov/variant.c 4 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/78795/1 diff --git a/src/mainboard/google/brya/variants/craaskov/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/Makefile.inc index f3987ab..7250b58 100644 --- a/src/mainboard/google/brya/variants/craaskov/Makefile.inc +++ b/src/mainboard/google/brya/variants/craaskov/Makefile.inc @@ -2,4 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c -ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/craaskov/fw_config.c b/src/mainboard/google/brya/variants/craaskov/fw_config.c new file mode 100644 index 0000000..800fc1f --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/fw_config.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 9cac704..8c29567 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -195,6 +195,14 @@ end end device ref pcie_rp7 off end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/craaskov/variant.c b/src/mainboard/google/brya/variants/craaskov/variant.c index 6a79780..68f128c 100644 --- a/src/mainboard/google/brya/variants/craaskov/variant.c +++ b/src/mainboard/google/brya/variants/craaskov/variant.c @@ -1,8 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <device/device.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; } + +void variant_devtree_update(void) +{ + struct device *emmc = DEV_PTR(emmc); + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + + if (!fw_config_is_provisioned()) { + printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "eMMC disabled by fw_config\n"); + emmc->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Gerrit-Change-Number: 78795 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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