coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78794?usp=email ) Change subject: mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2 ...................................................................... mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2 Intel has identified an idle hang issue on pre-prod silicon that will not be fixed or root-caused. To avoid the issue, this commit sets SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree. Note: This change will affect system power. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang on google/screebo. Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78794/1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 0835ded..7358eeb 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -52,6 +52,8 @@ register "cnvi_bt_core" = "true" register "sagv" = "SAGV_ENABLED" + # TODO(b/287170545): workaround avoid DUT random hang + register "sagv_wp_bitmap" = "SAGV_POINTS_0_1_2" register "sagv_freq_mhz[0]" = "3200" register "sagv_gear[0]" = "4" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 5894fe6..625a36b 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -49,6 +49,8 @@ register "cnvi_bt_core" = "true" register "sagv" = "SAGV_ENABLED" + # TODO(b/287170545): workaround avoid DUT random hang + register "sagv_wp_bitmap" = "SAGV_POINTS_0_1_2" register "sagv_freq_mhz[0]" = "3200" register "sagv_gear[0]" = "4" -- To view, visit https://review.coreboot.org/c/coreboot/+/78794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1 Gerrit-Change-Number: 78794 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: util/lint: Fix some mistakes in spelling.txt
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner, Martin L Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78822?usp=email ) Change subject: util/lint: Fix some mistakes in spelling.txt ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b53ce8538616c164efb4eb25ff859975ddadfd2 Gerrit-Change-Number: 78822 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Oct 2023 06:01:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78820?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8 Gerrit-Change-Number: 78820 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 06:00:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya/var/omnigul: Add fingerprint SPI
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Derek Huang, Jamie Chen, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78427?usp=email ) Change subject: mb/google/brya/var/omnigul: Add fingerprint SPI ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Gerrit-Change-Number: 78427 Gerrit-PatchSet: 9 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 05:56:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/dedede/var/pirika: Support for CXMT CXDB4CBAM-ML-A
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Anson Tseng, Daniel Peng, Karthik Ramasubramanian, Shou-Chieh Hsu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78792?usp=email ) Change subject: mb/google/dedede/var/pirika: Support for CXMT CXDB4CBAM-ML-A ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Gerrit-Change-Number: 78792 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 05:56:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/mendocino: Update FSP-S UPD to pass boot logo
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78817?usp=email ) Change subject: soc/amd/mendocino: Update FSP-S UPD to pass boot logo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78817?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie522956b6dfe2400ef91d43c80f2adc6d52c8415 Gerrit-Change-Number: 78817 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 31 Oct 2023 05:54:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/mendocino: Ensure MP2 disable soft fuse bit set properly
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78823?usp=email ) Change subject: soc/amd/mendocino: Ensure MP2 disable soft fuse bit set properly ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Gerrit-Change-Number: 78823 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 31 Oct 2023 05:54:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust Power State Current 2 threshold
by Eric Lai (Code Review) 31 Oct '23

31 Oct '23

Attention is currently required from: Eran Mitrani, Jérémy Compostella, Kapil Porwal, Shelley Chen, Tarun. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78653?usp=email ) Change subject: soc/intel/meteorlake: Adjust Power State Current 2 threshold ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78653?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Gerrit-Change-Number: 78653 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 05:53:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Disable FVM
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78662?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/screebo: Disable FVM ...................................................................... mb/google/rex/var/screebo: Disable FVM This patch disables FVM for IA and SA VRs as per the OEM requirement. BUG=b:307237761 TEST=Able to build and boot google/screebo. Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 0d69aca..b7ea555 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -40,6 +40,14 @@ .tdp_pl4 = 84, }" + # Override FVM and VR (IA and SA) configuration: Disable + register "enable_fast_vmode[VR_DOMAIN_IA]" = "0" + register "cep_enable[VR_DOMAIN_IA]" = "0" + register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "0" + register "enable_fast_vmode[VR_DOMAIN_SA]" = "0" + register "cep_enable[VR_DOMAIN_SA]" = "0" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb Gerrit-Change-Number: 78662 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mike Lee <mike5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Set Baseline Power Limit
by Subrata Banik (Code Review) 31 Oct '23

31 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78661?usp=email ) Change subject: mb/google/rex/var/screebo: Set Baseline Power Limit ...................................................................... mb/google/rex/var/screebo: Set Baseline Power Limit This patch allows google/rex mainboard to choose between "Performance" (PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs). This is important for platform to meet balance between power and performance. The OEM design google/screebo selects baseline power limit to maintain the balance performance in lower power. BUG=b:307237761 TEST=Able to build and boot google/screebo. w/o this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 57 Watts [INFO ] CPU PL4 = 114 Watts w/ this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 40 Watts [INFO ] CPU PL4 = 84 Watts Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c M src/mainboard/google/rex/variants/screebo/overridetree.cb 3 files changed, 63 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index e781f08..c162a44 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -238,4 +238,17 @@ config HAVE_SLP_S0_GATE def_bool n +choice + prompt "Choose desired processor power limits (PLs)" + default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO + default PL_PERFORMANCE + +config PL_PERFORMANCE + bool "Performance: Maximum PLs for maximum performance" + +config PL_BASELINE + bool "Baseline: Baseline PLs for balanced performance at lower power" + +endchoice + endif # BOARD_GOOGLE_REX_COMMON diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index d2adaae..02bdca5d 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -10,6 +10,7 @@ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) * Following values are for performance config as per document #640982 */ +#if CONFIG(PL_PERFORMANCE) const struct cpu_tdp_power_limits performance_efficient_limits[] = { { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, @@ -51,6 +52,49 @@ .pl4_power = 64000 }, }; +#else +const struct cpu_tdp_power_limits performance_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits power_optimized_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; +#endif void variant_devtree_update(void) { diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 06f7b9b..0d69aca 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -34,6 +34,12 @@ chip soc/intel/meteorlake + register "power_limits_config[MTL_P_282_242_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 40, + .tdp_pl4 = 84, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d Gerrit-Change-Number: 78661 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mike Lee <mike5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2023