coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: spd.h: Move enum ddr4_module_type to ddr4.h
by Jakub Czapiga (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Elyes Haouas. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71660 ) Change subject: spd.h: Move enum ddr4_module_type to ddr4.h ...................................................................... Patch Set 1: (1 comment) File src/include/device/dram/ddr4.h: https://review.coreboot.org/c/coreboot/+/71660/comment/0ef4c66f_ba223ed3 PS1, Line 61: typedef u8 spd_raw_data[512]; This is defined in ddr4.h as well as in ddr3.h -- To view, visit https://review.coreboot.org/c/coreboot/+/71660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4701af23af280055cea2795a3dd835243e7a4b47 Gerrit-Change-Number: 71660 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 04 Jan 2023 17:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/system76/adl-p: Add CPU PCIe RP RTD3 configs
by Tim Crawford (Code Review) 04 Jan '23

04 Jan '23

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71661 ) Change subject: mb/system76/adl-p: Add CPU PCIe RP RTD3 configs ...................................................................... mb/system76/adl-p: Add CPU PCIe RP RTD3 configs Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - System still asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` still increases after suspend Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/adl-p/variants/darp8/overridetree.cb M src/mainboard/system76/adl-p/variants/galp6/overridetree.cb 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/71661/1 diff --git a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb index 4a554ad..4caed3a 100644 --- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb @@ -22,6 +22,12 @@ .clk_req = 0, .flags = PCIE_RP_LTR, }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# + register "srcclk_pin" = "0" # SSD2_CLKREQ# + device generic 0 on end + end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb index fc93fdc..e63e185 100644 --- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -20,6 +20,12 @@ .clk_req = 0, .flags = PCIE_RP_LTR, }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST# + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" -- To view, visit https://review.coreboot.org/c/coreboot/+/71661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995 Gerrit-Change-Number: 71661 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Update vboot submodule to upstream main
by build bot (Jenkins) (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71582 ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 5: Verified-1 (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167626): https://review.coreboot.org/c/coreboot/+/71582/comment/bcc31fc5_2379fe9e PS5, Line 13: Fix: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167626): https://review.coreboot.org/c/coreboot/+/71582/comment/b35e7a43_2a237ede PS5, Line 14: cc1: error: firmware/lib/cryptolib/include: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4 Gerrit-Change-Number: 71582 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:55:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: libpayload/string: add strndup() function
by Jakub Czapiga (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Nico Huber, Thomas Heijligen, Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70115 ) Change subject: libpayload/string: add strndup() function ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/libc/string.c: https://review.coreboot.org/c/coreboot/+/70115/comment/f4ec1fe6_9e4c11e3 PS2, Line 333: size_t n = strlen(s); > Doesn't this defeat the point of strndup() (which is to not risk overrunning the buffer if the input […] Perhaps Thomas wanted to use `strnlen()` as it's done in glibc (https://codebrowser.dev/glibc/glibc/string/strndup.c.html) -- To view, visit https://review.coreboot.org/c/coreboot/+/70115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3 Gerrit-Change-Number: 70115 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:48:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Define a more suitable MRC training text message
by Jakub Czapiga (Code Review) 04 Jan '23

04 Jan '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70796 ) ( 26 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya: Define a more suitable MRC training text message ...................................................................... mb/google/brya: Define a more suitable MRC training text message This message is designed to reduce end-user confusion who may not know what memory training is. It also provides a maximum time estimation calibrated for brya devices. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=New message observed on skolas Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796 Reviewed-by: Anil Kumar K <anil.kumar.k(a)intel.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Anil Kumar K: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index bc754be..a267946 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -332,4 +332,7 @@ int default 32 +config MEMORY_TRAINING_TEXT + default "Your device is finishing an update. This may take 1-2 minutes.\\Please do not turn off your device." + endif # BOARD_GOOGLE_BRYA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/70796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Gerrit-Change-Number: 70796 Gerrit-PatchSet: 28 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya: Add romstage early graphics for brya
by Jakub Czapiga (Code Review) 04 Jan '23

04 Jan '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70304 ) Change subject: mb/google/brya: Add romstage early graphics for brya ...................................................................... mb/google/brya: Add romstage early graphics for brya BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/gma-mainboard.ads M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 3 files changed, 63 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index c40f21c..ab80e32 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -4,6 +4,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads new file mode 100644 index 0000000..3b02f14 --- /dev/null +++ b/src/mainboard/google/brya/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 70e7779..efc2fcb 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -123,7 +123,37 @@ }" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/70304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Gerrit-Change-Number: 70304 Gerrit-PatchSet: 43 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
by Nick Vaccaro (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Ren Kuo, Nick Vaccaro. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71628 ) Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/kano/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71628/comment/6fd619c7_1f4b7747 PS1, Line 20: option UFC_MIPI_OVTI2740 0 How does the firmware know whether to use ZYDRON_UFC to determine UFC type or use UFC to determine UFC type? I've never seen it done this way. -- To view, visit https://review.coreboot.org/c/coreboot/+/71628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46fac6c820d6006956680a07198db82225630905 Gerrit-Change-Number: 71628 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71647 ) Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71647/comment/be66865b_b1c113c8 PS2, Line 6: > > Possible long commit subject (prefer a maximum 65 characters) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Chris Wang, Martin Roth. Hello build bot (Jenkins), Dtrain Hsu, Jason Nien, Jason Glenesk, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71647 to look at the new patch set (#6). Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun ...................................................................... mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/71647/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for PCIe a...
by Jason Glenesk (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Chris Wang, Martin Roth. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71647 ) Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for PCIe advisory ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:23:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023