Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71638 )
Change subject: mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
......................................................................
mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required
to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig
option, CSE reboots the system into CSE_RW FW region on cold reboot.
BUG=b:224325352
TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe
CSE boot to RW FW region as part of coreboot console log,
localhost ~ # cbmem -c | grep cse
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 28 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Sridhar Siricilla: Looks good to me, approved
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 349e9de..9d8982d 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -4,6 +4,7 @@
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE
config BOARD_INTEL_MTLRVP_P
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Change subject: mb/intel/mtlrvp: Configure USB devices for MTL-RVP
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Please do help in progressing the CL
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Change subject: mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please do help in progressing the CL.
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Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71170/comment/f833e524_97451299
PS9, Line 15: frome
> from
fixed.
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Hello build bot (Jenkins), David Wu, Tarun Tuli, Martin L Roth, Dtrain Hsu, Kangheui Won, Reka Norman, Tyler Wang, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71170
to look at the new patch set (#10).
Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe
......................................................................
mb/google/nissa/var/craask: Modify GPIOs for NVMe
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for
commonality of GPIO settings. To reserve craask GPIO table and add
craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will
be 2 and clksrc is still 1.
BUG=b:259211172
TEST=Verify on reworked craask DUT to boot up from NVMe.
Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/craask/fw_config.c
M src/mainboard/google/brya/variants/craask/gpio.c
M src/mainboard/google/brya/variants/craask/overridetree.cb
3 files changed, 25 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/71170/10
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71641 )
Change subject: mb/google/brya/var/skolas: Set tcc_offset value to 3
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71641/comment/d93f5717_1878d821
PS1, Line 9: TCC circuit trip temperature
Thermal Control Circuit (TCC)?
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Change subject: mb/google/brya/var/marasov: Disable FPMCU interface
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/mainboard/google/brya/variants/marasov/gpio.c:
https://review.coreboot.org/c/coreboot/+/71650/comment/92da1bb7_21545696
PS7, Line 104: GPP_F11
> Should it be PAD_NC_LOCK? Same as GPP_F12, GPP_F13, GPP_F15, GPP_F16.
Done
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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/meteorlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/64561/comment/21706002_dc04ff7a
PS9, Line 158: #if CONFIG(SOFTWARE_CONNECTION_MANAGER)
> unlike ADL/TGL, SCM is always disabled for MTL. Is this expected?
we have to select this for MTL
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Change subject: mb/google/brya/var/marasov: Update DPTF parameters
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/meteorlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/64561/comment/779ef39a_95be09d9
PS9, Line 158: #if CONFIG(SOFTWARE_CONNECTION_MANAGER)
unlike ADL/TGL, SCM is always disabled for MTL. Is this expected?
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