coreboot-gerrit January 2023

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[M] Change in coreboot[master]: spd.h: Move enum ddr4_module_type to ddr4.h
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71660 ) Change subject: spd.h: Move enum ddr4_module_type to ddr4.h ...................................................................... spd.h: Move enum ddr4_module_type to ddr4.h Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: I4701af23af280055cea2795a3dd835243e7a4b47 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/ddr4.h M src/include/spd.h M src/mainboard/scaleway/tagada/ramstage.c M tests/lib/dimm_info_util-test.c 6 files changed, 30 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/71660/1 diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 050857e..3b261a2 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -272,25 +272,7 @@ dimm->dimm_num = slot; memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); dimm->mod_id = info->manufacturer_id; - - switch (info->dimm_type) { - case SPD_DDR4_DIMM_TYPE_SO_DIMM: - dimm->mod_type = DDR4_SPD_SODIMM; - break; - case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = DDR4_SPD_72B_SO_RDIMM; - break; - case SPD_DDR4_DIMM_TYPE_UDIMM: - dimm->mod_type = DDR4_SPD_UDIMM; - break; - case SPD_DDR4_DIMM_TYPE_RDIMM: - dimm->mod_type = DDR4_SPD_RDIMM; - break; - default: - dimm->mod_type = SPD_UNDEFINED; - break; - } - + dimm->mod_type = info->dimm_type; dimm->bus_width = info->bus_width; memcpy(dimm->serial, info->serial_number, MIN(sizeof(dimm->serial), sizeof(info->serial_number))); diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index cfaf86f..4eec47b 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <device/dram/spd.h> #include <spd.h> #include <stddef.h> @@ -106,22 +107,22 @@ } } -static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type, +static void convert_ddr4_module_type_to_spd_info(enum spd_dimm_type_ddr4 module_type, struct spd_info *info) { switch (module_type) { - case DDR4_SPD_RDIMM: - case DDR4_SPD_MINI_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_RIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR4_SPD_UDIMM: - case DDR4_SPD_MINI_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR4_SPD_SODIMM: - case DDR4_SPD_72B_SO_UDIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index ee7a1ea..d9c4f22 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -21,10 +21,7 @@ #define SPD_DDR4_PART_OFF 329 #define SPD_DDR4_PART_LEN 20 -/* - * Module type (byte 3, bits 3:0) of SPD - * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. - */ +/* Byte 3 [3:0]: DDR4 Module type information */ enum spd_dimm_type_ddr4 { SPD_DDR4_DIMM_TYPE_EXTENDED = 0x0, SPD_DDR4_DIMM_TYPE_RDIMM = 0x1, diff --git a/src/include/spd.h b/src/include/spd.h index 2fe9f96..9dc10aa 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,20 +201,6 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3 [3:0]: DDR4 Module type information */ -enum ddr4_module_type { - DDR4_SPD_RDIMM = 0x01, - DDR4_SPD_UDIMM = 0x02, - DDR4_SPD_SODIMM = 0x03, - DDR4_SPD_LRDIMM = 0x04, - DDR4_SPD_MINI_RDIMM = 0x05, - DDR4_SPD_MINI_UDIMM = 0x06, - DDR4_SPD_72B_SO_RDIMM = 0x08, - DDR4_SPD_72B_SO_UDIMM = 0x09, - DDR4_SPD_16B_SO_DIMM = 0x0c, - DDR4_SPD_32B_SO_RDIMM = 0x0d, -}; - enum ddr5_module_type { DDR5_SPD_RDIMM = 0x01, DDR5_SPD_UDIMM = 0x02, diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c index bb0a385..ca91b32 100644 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ b/src/mainboard/scaleway/tagada/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/dram/ddr4.h> #include <string.h> #include <fsp/api.h> #include <soc/ramstage.h> @@ -83,5 +84,5 @@ int channel, int dimm, int index) { /* Mainboard only has DDR4 DIMM slots */ - mem_info->dimm[index].mod_type = DDR4_SPD_UDIMM; + mem_info->dimm[index].mod_type = SPD_DDR4_DIMM_TYPE_UDIMM; } diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 43fe6c9..9615077 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <dimm_info_util.h> #include <spd.h> #include <tests/test.h> @@ -156,9 +157,11 @@ }, { .memory_type = MEMORY_TYPE_DDR4, - .udimm_allowed = {DDR4_SPD_UDIMM, DDR4_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR4_SPD_RDIMM, DDR4_SPD_MINI_RDIMM}, - .expected_module_type = DDR4_SPD_SODIMM, + .udimm_allowed = {SPD_DDR4_DIMM_TYPE_UDIMM, + SPD_DDR4_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR4_DIMM_TYPE_RDIMM, + SPD_DDR4_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR4_DIMM_TYPE_SO_DIMM, }, {.memory_type = MEMORY_TYPE_DDR5, .udimm_allowed = {DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM}, -- To view, visit https://review.coreboot.org/c/coreboot/+/71660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4701af23af280055cea2795a3dd835243e7a4b47 Gerrit-Change-Number: 71660 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values...
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Angel Pons, Jincheng Li, Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71633 ) Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Gerrit-Change-Number: 71633 Gerrit-PatchSet: 2 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 12:44:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd.h: Move enum ddr3_module_type to ddr3.h
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71547 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spd.h: Move enum ddr3_module_type to ddr3.h ...................................................................... spd.h: Move enum ddr3_module_type to ddr3.h Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/dram/ddr3.c M src/device/dram/spd.c M src/include/device/dram/ddr3.h M src/include/spd.h M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M tests/lib/dimm_info_util-test.c 7 files changed, 37 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 2bdfd46..9e11ab5 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -533,29 +533,7 @@ dimm->dimm_num = slot; memcpy(dimm->module_part_number, info->part_number, 16); dimm->mod_id = info->manufacturer_id; - - switch (info->dimm_type) { - case SPD_DDR3_DIMM_TYPE_SO_DIMM: - dimm->mod_type = DDR3_SPD_SODIMM; - break; - case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: - dimm->mod_type = DDR3_SPD_72B_SO_CDIMM; - break; - case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = DDR3_SPD_72B_SO_RDIMM; - break; - case SPD_DDR3_DIMM_TYPE_UDIMM: - dimm->mod_type = DDR3_SPD_UDIMM; - break; - case SPD_DDR3_DIMM_TYPE_RDIMM: - dimm->mod_type = DDR3_SPD_RDIMM; - break; - case SPD_DDR3_DIMM_TYPE_UNDEFINED: - default: - dimm->mod_type = SPD_UNDEFINED; - break; - } - + dimm->mod_type = info->dimm_type; dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only memcpy(dimm->serial, info->serial, MIN(sizeof(dimm->serial), sizeof(info->serial))); diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index 738c05b..cfaf86f 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <device/dram/ddr2.h> +#include <device/dram/ddr3.h> #include <device/dram/spd.h> #include <spd.h> #include <stddef.h> @@ -76,26 +77,26 @@ } } -static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type, +static void convert_ddr3_module_type_to_spd_info(enum spd_dimm_type_ddr3 module_type, struct spd_info *info) { switch (module_type) { - case DDR3_SPD_RDIMM: - case DDR3_SPD_MINI_RDIMM: + case SPD_DDR3_DIMM_TYPE_RDIMM: + case SPD_DDR3_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_RIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR3_SPD_UDIMM: - case DDR3_SPD_MINI_UDIMM: + case SPD_DDR3_DIMM_TYPE_UDIMM: + case SPD_DDR3_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR3_SPD_MICRO_DIMM: + case SPD_DDR3_DIMM_TYPE_MICRO_DIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; - case DDR3_SPD_SODIMM: - case DDR3_SPD_72B_SO_UDIMM: + case SPD_DDR3_DIMM_TYPE_SO_DIMM: + case SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; @@ -216,7 +217,7 @@ return SPD_DDR2_DIMM_TYPE_RDIMM; case MEMORY_FORMFACTOR_SODIMM: module_type = (memory_type == MEMORY_TYPE_DDR2) ? SPD_DDR2_DIMM_TYPE_SO_DIMM : - DDR3_SPD_SODIMM; + SPD_DDR3_DIMM_TYPE_SO_DIMM; return module_type; default: return convert_default_form_factor_to_module_type(); diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index b109a15..8886e64 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -32,10 +32,7 @@ #define SPD_DIMM_PART_LEN 18 /** @} */ -/* - * Module type (byte 3, bits 3:0) of SPD - * This definition is specific to DDR3. DDR2 SPDs have a different structure. - */ +/* Byte 3 [3:0]: DDR3 Module type information */ enum spd_dimm_type_ddr3 { SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00, SPD_DDR3_DIMM_TYPE_RDIMM = 0x01, diff --git a/src/include/spd.h b/src/include/spd.h index 25d0463..2fe9f96 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,23 +201,6 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3 [3:0]: DDR3 Module type information */ -enum ddr3_module_type { - DDR3_SPD_RDIMM = 0x01, - DDR3_SPD_UDIMM = 0x02, - DDR3_SPD_SODIMM = 0x03, - DDR3_SPD_MICRO_DIMM = 0x04, - DDR3_SPD_MINI_RDIMM = 0x05, - DDR3_SPD_MINI_UDIMM = 0x06, - DDR3_SPD_MINI_CDIMM = 0x07, - DDR3_SPD_72B_SO_UDIMM = 0x08, - DDR3_SPD_72B_SO_RDIMM = 0x09, - DDR3_SPD_72B_SO_CDIMM = 0x0a, - DDR3_SPD_LRDIMM = 0x0b, - DDR3_SPD_16B_SO_DIMM = 0x0c, - DDR3_SPD_32B_SO_RDIMM = 0x0d, -}; - /* Byte 3 [3:0]: DDR4 Module type information */ enum ddr4_module_type { DDR4_SPD_RDIMM = 0x01, diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 5336769..7adae9e 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -261,7 +261,7 @@ dimm->mod_id = (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a308d07..aec300b 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -433,7 +433,7 @@ dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } @@ -457,7 +457,7 @@ dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index e16f441..43fe6c9 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/dram/ddr2.h> +#include <device/dram/ddr3.h> #include <dimm_info_util.h> #include <spd.h> #include <tests/test.h> @@ -146,10 +147,12 @@ }, { .memory_type = MEMORY_TYPE_DDR3, - .udimm_allowed = {DDR3_SPD_UDIMM, DDR3_SPD_MICRO_DIMM, - DDR3_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR3_SPD_RDIMM, DDR3_SPD_MINI_RDIMM}, - .expected_module_type = DDR3_SPD_SODIMM, + .udimm_allowed = {SPD_DDR3_DIMM_TYPE_UDIMM, + SPD_DDR3_DIMM_TYPE_MICRO_DIMM, + SPD_DDR3_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR3_DIMM_TYPE_RDIMM, + SPD_DDR3_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR3_DIMM_TYPE_SO_DIMM, }, { .memory_type = MEMORY_TYPE_DDR4, -- To view, visit https://review.coreboot.org/c/coreboot/+/71547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Gerrit-Change-Number: 71547 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl1: Limit SATA speed to Gen 2
by Mario Scheithauer (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71230 ) Change subject: mb/siemens/mc_ehl1: Limit SATA speed to Gen 2 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Gerrit-Change-Number: 71230 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 11:39:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Make SATA speed limit configurable
by Mario Scheithauer (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Paul Menzel, Lean Sheng Tan, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71229 ) Change subject: soc/intel/elkhartlake: Make SATA speed limit configurable ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/intel/elkhartlake/chip.h: https://review.coreboot.org/c/coreboot/+/71229/comment/42b0997e_0787e49e PS2, Line 108: SATA_DEFAULT = 0, : SATA_GEN1, : SATA_GEN2 > Since Gen 3 is the highest SATA speed grade it is not really a limit then. […] I have also looked inside FSP and there it is defined as you already mentioned. So I just thought that maybe it's good to keep it the same, but it's good for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/71229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Gerrit-Change-Number: 71229 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 11:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Make SATA speed limit configurable
by Werner Zeh (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Paul Menzel, Mario Scheithauer, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71229 ) Change subject: soc/intel/elkhartlake: Make SATA speed limit configurable ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/elkhartlake/chip.h: https://review.coreboot.org/c/coreboot/+/71229/comment/1394f89e_4a8c70dc PS2, Line 108: SATA_DEFAULT = 0, : SATA_GEN1, : SATA_GEN2 > Should you also list 'SATA_GEN3' for the completeness? Since Gen 3 is the highest SATA speed grade it is not really a limit then. In addition, inside FSP, Gen 3 is treated the same way default is. Therefore, I have not added Gen 3 to this list. -- To view, visit https://review.coreboot.org/c/coreboot/+/71229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Gerrit-Change-Number: 71229 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 11:28:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Configure USB devices for MTL-RVP
by Harsha B R (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jamie Ryu, Subrata Banik, Eric Lai, Usha P. Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71168 to look at the new patch set (#5). Change subject: mb/intel/mtlrvp: Configure USB devices for MTL-RVP ...................................................................... mb/intel/mtlrvp: Configure USB devices for MTL-RVP This patch adds OC configuration of USB devices for MTL-RVP as per MTL-RVP design specification, USB 2.0 usb2_ports0 -> OC0 usb2_ports1 -> OC0 usb2_ports2 -> OC0 usb2_ports3 -> OC0 usb2_ports4 -> OC0 usb2_ports5 -> OC0 usb2_ports6 -> OC_SKIP usb2_ports7 -> OC_SKIP usb2_ports8 -> OC_SKIP usb2_ports9 -> OC_SKIP USB 3.2 Gen 2x1 usb3_ports0 -> OC0 usb3_ports1 -> OC0 TCPx tcss_ports0 -> OC0 tcss_ports1 -> OC0 tcss_ports2 -> OC0 tcss_ports3 -> OC0 BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS (on top of CB: 66190). Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71168/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/71168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Gerrit-Change-Number: 71168 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by John Su (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Nien, Martin Roth. John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71619 ) Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... mb/google/skyrim/var/markarth: Update RAM ID table Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc M src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt M src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt 3 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/71619/1 diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc index 258a35b..7ddd1cc 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc @@ -4,5 +4,5 @@ # ./util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/markarth/memory src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068, MT62F1G32D2DS-026 WT:B SPD_SOURCES += spd/lp5/set-1/spd-8.hex # ID = 1(0b0001) Parts = K3KL9L90CM-MGCT, H58G66BK7BX067, MT62F2G32D4DS-026 WT:B diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt index c2ca506..fd2a1cb 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt +++ b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt @@ -6,6 +6,7 @@ DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt index cded20f..2991b9c 100644 --- a/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt +++ b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt @@ -3,3 +3,4 @@ K3KL9L90CM-MGCT, H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, +MT62F1G32D2DS-026 WT:B, -- To view, visit https://review.coreboot.org/c/coreboot/+/71619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Gerrit-Change-Number: 71619 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: intelblocks/cse: Add functions to check and change PTT state
by Sridhar Siricilla (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Michał Żygowski, Michał Kopeć. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68919 ) Change subject: intelblocks/cse: Add functions to check and change PTT state ...................................................................... Patch Set 3: (10 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/68919/comment/d0fe4217_bcf6c692 PS3, Line 1078: int enum cb_err https://review.coreboot.org/c/coreboot/+/68919/comment/38109e47_0820736c PS3, Line 1099: feature_status fw_runtime_status? https://review.coreboot.org/c/coreboot/+/68919/comment/c7f65b5f_0af470d3 PS3, Line 1123: 0 CB_ERR? https://review.coreboot.org/c/coreboot/+/68919/comment/8e4dcb0a_0401db1b PS3, Line 1127: 0 CB_ERR? https://review.coreboot.org/c/coreboot/+/68919/comment/846bbdf2_355a1ff3 PS3, Line 1132: ; CB_ERR? https://review.coreboot.org/c/coreboot/+/68919/comment/e8cb72bd_2f7c734c PS3, Line 1137: return 1; CB_SUCCESS? https://review.coreboot.org/c/coreboot/+/68919/comment/3d43bb0a_fe868d41 PS3, Line 1158: HMRFPO Enable FW FEATURE SHIPMENT TIME STATE OVERRIDE ? https://review.coreboot.org/c/coreboot/+/68919/comment/07e573e7_06872228 PS3, Line 1180: HFSTS1 FW Inti Complete is set 5) Before EOP issued to CSE It is good to add the condition for completeness though the API doesn't verifies. Agree? https://review.coreboot.org/c/coreboot/+/68919/comment/f98b8641_db7ccc29 PS3, Line 1189: cse_get_fw_feature_state Need to update the if condition based on my comments (cb_success:0. cb_err:non_zero) . File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/68919/comment/461084f7_ece4cc80 PS3, Line 574: Returns 0 on failure and 1 on success. This needs update. -- To view, visit https://review.coreboot.org/c/coreboot/+/68919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Gerrit-Change-Number: 68919 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 11:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
by Sridhar Siricilla (Code Review) 04 Jan '23

04 Jan '23

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71638 ) Change subject: mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Please do help in progressing the CL. done. -- To view, visit https://review.coreboot.org/c/coreboot/+/71638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd Gerrit-Change-Number: 71638 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 10:58:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: comment

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