coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for PCIe a...
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Hello build bot (Jenkins), Dtrain Hsu, Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71647 to look at the new patch set (#5). Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for PCIe advisory ...................................................................... mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for PCIe advisory Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/71647/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/fch_spi: Inline spi_bar read and writes
by Fred Reitberger (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71563 ) Change subject: soc/amd/fch_spi: Inline spi_bar read and writes ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71563/comment/c9c0ea2c_a2e15c50 PS1, Line 25: 16-19ms > That's crazy... Why? Was calling a function really that expensive? […] Looks like these util functions are still used in a few other files (fch_spi.c and glinda/mendocino/morgana espi_util.c from a quick grep search), though it would be nice if they all could be inlined. Is there much of a speed difference on warm boots where the APOB is not rewritten? -- To view, visit https://review.coreboot.org/c/coreboot/+/71563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eb3ddfd4e3e88e10b4aa61e8e99f5323c8922af Gerrit-Change-Number: 71563 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:20:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/fch_spi: Inline spi_bar read and writes
by Raul Rangel (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Arthur Heymans, Martin Roth, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71563 ) Change subject: soc/amd/fch_spi: Inline spi_bar read and writes ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71563/comment/1d7f941a_da296925 PS1, Line 25: 16-19ms That's crazy... Why? Was calling a function really that expensive? Does soc/amd/common/block/spi/fch_spi_util.c still serve a purpose? -- To view, visit https://review.coreboot.org/c/coreboot/+/71563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eb3ddfd4e3e88e10b4aa61e8e99f5323c8922af Gerrit-Change-Number: 71563 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Jan 2023 16:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: contributing/coding_style.md: Add and clarify includes rules
by Julius Werner (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Nico Huber, Martin L Roth, Paul Menzel, Arthur Heymans, Elyes Haouas. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71612 ) Change subject: contributing/coding_style.md: Add and clarify includes rules ...................................................................... Patch Set 1: (4 comments) File Documentation/contributing/coding_style.md: https://review.coreboot.org/c/coreboot/+/71612/comment/dd292364_fe2ee5d3 PS1, Line 921: Local "file.h" includes should always come separately after all : <file.h> includes Order of local vs. system includes is already mentioned here. If you want to start making <vendorcode> a separate group (do we want that? Why?) you could add it here. https://review.coreboot.org/c/coreboot/+/71612/comment/4409cf24_7b52135a PS1, Line 925: The includes should be ordered alphabetically. Last time there was a big fight about this I think we decided that we don't want to mandate it. https://review.coreboot.org/c/coreboot/+/71612/comment/30bdb0c0_178503ff PS1, Line 927: Don't use UNIX directory '.' or '..' shortcuts and put conditional includes This doesn't really match existing practice in coreboot (e.g. mainboard directories often contain local headers that are included via double-quote paths, as explicitly allowed in the second sentence of this paragraph, and in cases where those headers are one directory up you have to use '..'). https://review.coreboot.org/c/coreboot/+/71612/comment/d7a64454_f8b64d93 PS1, Line 933: #ifdef CONDITION Honestly, I think conditionally including files is a pretty bad practice in general and we should just avoid it completely wherever possible. So I'm not sure it's a good idea to explicitly list that case here. -- To view, visit https://review.coreboot.org/c/coreboot/+/71612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3af2c3b15dda7e8b095767084dae8ee24d478256 Gerrit-Change-Number: 71612 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 04 Jan 2023 15:55:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update vboot submodule to upstream main
by Julius Werner (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Elyes Haouas. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71582 ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4 Gerrit-Change-Number: 71582 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 04 Jan 2023 15:19:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCI...
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71647 ) Change subject: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71647/comment/53be45a4_51655ef3 PS2, Line 7: mb/goog > remove? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 15:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCI...
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Nien, Chris Wang, Martin Roth. Hello build bot (Jenkins), Dtrain Hsu, Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71647 to look at the new patch set (#4). Change subject: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization ...................................................................... mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/71647/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCI...
by Chris Wang (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Nien, Chris Wang, Martin Roth. Hello build bot (Jenkins), Dtrain Hsu, Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71647 to look at the new patch set (#3). Change subject: mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization ...................................................................... mb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/71647/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/fch_spi: Inline spi_bar read and writes
by Fred Reitberger (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71563 ) Change subject: soc/amd/fch_spi: Inline spi_bar read and writes ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eb3ddfd4e3e88e10b4aa61e8e99f5323c8922af Gerrit-Change-Number: 71563 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Jan 2023 14:38:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Create common function to check PCH slot
by Jakub Czapiga (Code Review) 04 Jan '23

04 Jan '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71236 ) Change subject: soc/intel: Create common function to check PCH slot ...................................................................... soc/intel: Create common function to check PCH slot BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/irq.h M src/soc/intel/common/block/irq/irq.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 117 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 08108f4..7c3ad91 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -429,7 +429,7 @@ /* Count PCH devices */ while (entry) { - if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) + if (is_pch_slot(entry->devfn)) ++pch_total; entry = entry->next; } @@ -438,7 +438,7 @@ config = calloc(pch_total, sizeof(*config)); entry = get_cached_pci_irqs(); while (entry) { - if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { + if (!is_pch_slot(entry->devfn)) { entry = entry->next; continue; } diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 7051f51..c9ef548 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -298,7 +298,7 @@ /* Count PCH devices */ while (entry) { - if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) + if (is_pch_slot(entry->devfn)) ++pch_total; entry = entry->next; } @@ -307,7 +307,7 @@ config = calloc(pch_total, sizeof(*config)); entry = get_cached_pci_irqs(); while (entry) { - if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { + if (!is_pch_slot(entry->devfn)) { entry = entry->next; continue; } diff --git a/src/soc/intel/common/block/include/intelblocks/irq.h b/src/soc/intel/common/block/include/intelblocks/irq.h index 33c9b7e..3945e3e7 100644 --- a/src/soc/intel/common/block/include/intelblocks/irq.h +++ b/src/soc/intel/common/block/include/intelblocks/irq.h @@ -66,4 +66,10 @@ return the corresponding IRQ, or INVALID_IRQ if not found. */ int get_pci_devfn_irq(unsigned int devfn); +/* Check if a given slot is a PCH slot. + * Note: For PCH less SoC platforms, like MeteorLake and onwards, this function + * can be utilized to check if a slot belongs to the SoC or IOE die. + */ +bool is_pch_slot(unsigned int devfn); + #endif /* SOC_INTEL_COMMON_IRQ_H */ diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index 8b0642f..724061e 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -404,6 +404,13 @@ return true; } +bool __weak is_pch_slot(unsigned int devfn) +{ + if (PCI_SLOT(devfn) >= MIN_PCH_SLOT) + return true; + return false; +} + bool irq_program_non_pch(void) { const struct pci_irq_entry *entry = cached_entries; @@ -412,7 +419,7 @@ return false; while (entry) { - if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) { + if (is_pch_slot(entry->devfn)) { entry = entry->next; continue; } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 13c5fc0..f67e205 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -269,7 +269,7 @@ /* Count PCH devices */ while (entry) { - if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) + if (is_pch_slot(entry->devfn)) ++pch_total; entry = entry->next; } @@ -278,7 +278,7 @@ config = calloc(pch_total, sizeof(*config)); entry = get_cached_pci_irqs(); while (entry) { - if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { + if (!is_pch_slot(entry->devfn)) { entry = entry->next; continue; } -- To view, visit https://review.coreboot.org/c/coreboot/+/71236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Gerrit-Change-Number: 71236 Gerrit-PatchSet: 7 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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