coreboot-gerrit January 2023

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Disable FPMCU interface
by Frank Chu (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71650 to look at the new patch set (#3). Change subject: mb/google/brya/var/marasov: Disable FPMCU interface ...................................................................... mb/google/brya/var/marasov: Disable FPMCU interface Set unused fingerprint GPIO to NC for meet HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e --- M src/mainboard/google/brya/variants/marasov/gpio.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/71650/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Gerrit-Change-Number: 71650 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: update GPIO for unused FP PIN
by Frank Chu (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71650 to look at the new patch set (#2). Change subject: mb/google/brya/var/marasov: update GPIO for unused FP PIN ...................................................................... mb/google/brya/var/marasov: update GPIO for unused FP PIN set unused fingerprint GPIO to NC. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e --- M src/mainboard/google/brya/variants/marasov/gpio.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/71650/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Gerrit-Change-Number: 71650 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: update GPIO for unused FP PIN
by Frank Chu (Code Review) 04 Jan '23

04 Jan '23

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71650 ) Change subject: mb/google/brya/var/marasov: update GPIO for unused FP PIN ...................................................................... mb/google/brya/var/marasov: update GPIO for unused FP PIN set unused fingerprint GPIO to NA. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e --- M src/mainboard/google/brya/variants/marasov/gpio.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/71650/1 diff --git a/src/mainboard/google/brya/variants/marasov/gpio.c b/src/mainboard/google/brya/variants/marasov/gpio.c index 032922a..4608c2d 100644 --- a/src/mainboard/google/brya/variants/marasov/gpio.c +++ b/src/mainboard/google/brya/variants/marasov/gpio.c @@ -100,6 +100,16 @@ PAD_NC(GPP_E21, NONE), /* F6 : WWAN_WLAN_COEX3 ==> NC */ PAD_NC(GPP_F6, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), /* F19 : GPP_F19(TP93) ==> NC */ PAD_NC(GPP_F19, NONE), /* F20 : UCAM_RST_L ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Gerrit-Change-Number: 71650 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/eltan/security/Makefile.inc: Remove path to non-existent directory
by Erik van den Bogaert (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Frans Hendriks, Elyes Haouas. Erik van den Bogaert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71298 ) Change subject: vc/eltan/security/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03 Gerrit-Change-Number: 71298 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 04 Jan 2023 07:26:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71613 ) Change subject: nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONS ...................................................................... nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONS Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71613 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/x4x/Kconfig 6 files changed, 23 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index aa03eac..adb0115 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -2,11 +2,6 @@ config NORTHBRIDGE_INTEL_E7505 bool - -if NORTHBRIDGE_INTEL_E7505 - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE @@ -16,5 +11,3 @@ select NO_DDR3 select NO_DDR2 select SMM_TSEG - -endif diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 0b0ff5162..39e15ad 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -2,11 +2,6 @@ config NORTHBRIDGE_INTEL_GM45 bool - -if NORTHBRIDGE_INTEL_GM45 - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select HAVE_DEBUG_RAM_SETUP select VGA select INTEL_EDID @@ -19,6 +14,8 @@ select USE_DDR3 select USE_DDR2 +if NORTHBRIDGE_INTEL_GM45 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d1e7dbe..33fb184 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -2,11 +2,6 @@ config NORTHBRIDGE_INTEL_I945 bool - -if NORTHBRIDGE_INTEL_I945 - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select HAVE_DEBUG_RAM_SETUP select VGA select INTEL_GMA_ACPI @@ -19,6 +14,8 @@ select NO_DDR3 select USE_DDR2 +if NORTHBRIDGE_INTEL_I945 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK config NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 7ece198..5714b4f 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -2,11 +2,6 @@ config NORTHBRIDGE_INTEL_PINEVIEW bool - -if NORTHBRIDGE_INTEL_PINEVIEW - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select HAVE_DEBUG_RAM_SETUP select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT @@ -19,6 +14,8 @@ select USE_DDR3 select USE_DDR2 +if NORTHBRIDGE_INTEL_PINEVIEW + config VGA_BIOS_ID string default "8086,a001" diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index bbe8ac4..384d5bc 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -6,17 +6,14 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI - -if NORTHBRIDGE_INTEL_SANDYBRIDGE - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select NO_DDR5 select NO_LPDDR4 select NO_DDR4 select NO_DDR2 select USE_DDR3 +if NORTHBRIDGE_INTEL_SANDYBRIDGE + config CHIPSET_DEVICETREE default "northbridge/intel/sandybridge/chipset.cb" diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index a548df2..aef9eb4 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -2,11 +2,6 @@ config NORTHBRIDGE_INTEL_X4X bool - -if NORTHBRIDGE_INTEL_X4X - -config NORTHBRIDGE_SPECIFIC_OPTIONS - def_bool y select HAVE_DEBUG_RAM_SETUP select VGA select INTEL_GMA_ACPI @@ -19,6 +14,8 @@ select USE_DDR3 select USE_DDR2 +if NORTHBRIDGE_INTEL_X4X + config CBFS_SIZE default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -- To view, visit https://review.coreboot.org/c/coreboot/+/71613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5 Gerrit-Change-Number: 71613 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: spd.h: Move enum ddr2_module_type to ddr2.h
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71546 ) Change subject: spd.h: Move enum ddr2_module_type to ddr2.h ...................................................................... spd.h: Move enum ddr2_module_type to ddr2.h Move specific enum ddr2_module_type to <device/dram/ddr2.h>. Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/dram/spd.c M src/include/device/dram/ddr2.h M src/include/spd.h M tests/lib/dimm_info_util-test.c 4 files changed, 39 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index deff674..738c05b 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <device/dram/ddr2.h> #include <device/dram/spd.h> #include <spd.h> #include <stddef.h> @@ -47,25 +48,25 @@ info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; } -static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type, +static void convert_ddr2_module_type_to_spd_info(enum spd_dimm_type_ddr2 module_type, struct spd_info *info) { switch (module_type) { - case DDR2_SPD_RDIMM: - case DDR2_SPD_MINI_RDIMM: + case SPD_DDR2_DIMM_TYPE_RDIMM: + case SPD_DDR2_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_RIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR2_SPD_UDIMM: - case DDR2_SPD_MINI_UDIMM: + case SPD_DDR2_DIMM_TYPE_UDIMM: + case SPD_DDR2_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR2_SPD_MICRO_DIMM: + case SPD_DDR2_DIMM_TYPE_MICRO_DIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; - case DDR2_SPD_SODIMM: + case SPD_DDR2_DIMM_TYPE_SO_DIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; @@ -210,11 +211,11 @@ switch (form_factor) { case MEMORY_FORMFACTOR_DIMM: - return DDR2_SPD_UDIMM; + return SPD_DDR2_DIMM_TYPE_UDIMM; case MEMORY_FORMFACTOR_RIMM: - return DDR2_SPD_RDIMM; + return SPD_DDR2_DIMM_TYPE_RDIMM; case MEMORY_FORMFACTOR_SODIMM: - module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM : + module_type = (memory_type == MEMORY_TYPE_DDR2) ? SPD_DDR2_DIMM_TYPE_SO_DIMM : DDR3_SPD_SODIMM; return module_type; default: diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 6200fde..9277ffb 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -18,15 +18,12 @@ #include <spd.h> #include <device/dram/common.h> -/* - * Module type (byte 20, bits 5:0) of SPD - * This definition is specific to DDR2. DDR3 SPDs have a different structure. - */ +/* Byte 20 [5:0]: DDR2 Module type information */ enum spd_dimm_type_ddr2 { - SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, - SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, - SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, - SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08, diff --git a/src/include/spd.h b/src/include/spd.h index 7a6e5ab..25d0463 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,18 +201,6 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 20 [5:0]: DDR2 Module type information */ -enum ddr2_module_type { - DDR2_SPD_RDIMM = 0x01, - DDR2_SPD_UDIMM = 0x02, - DDR2_SPD_SODIMM = 0x04, - DDR2_SPD_72B_SO_CDIMM = 0x06, - DDR2_SPD_72B_SO_RDIMM = 0x07, - DDR2_SPD_MICRO_DIMM = 0x08, - DDR2_SPD_MINI_RDIMM = 0x10, - DDR2_SPD_MINI_UDIMM = 0x20, -}; - /* Byte 3 [3:0]: DDR3 Module type information */ enum ddr3_module_type { DDR3_SPD_RDIMM = 0x01, diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index cecbacb..e16f441 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/dram/ddr2.h> #include <dimm_info_util.h> #include <spd.h> #include <tests/test.h> @@ -136,10 +137,12 @@ } ddrx_info[] = { { .memory_type = MEMORY_TYPE_DDR2, - .udimm_allowed = {DDR2_SPD_UDIMM, DDR2_SPD_MICRO_DIMM, - DDR2_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR2_SPD_RDIMM, DDR2_SPD_MINI_RDIMM}, - .expected_module_type = DDR2_SPD_SODIMM, + .udimm_allowed = {SPD_DDR2_DIMM_TYPE_UDIMM, + SPD_DDR2_DIMM_TYPE_MICRO_DIMM, + SPD_DDR2_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR2_DIMM_TYPE_RDIMM, + SPD_DDR2_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR2_DIMM_TYPE_SO_DIMM, }, { .memory_type = MEMORY_TYPE_DDR3, -- To view, visit https://review.coreboot.org/c/coreboot/+/71546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Gerrit-Change-Number: 71546 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/ironlake: Specify supported memory type
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71584 ) Change subject: nb/intel/ironlake: Specify supported memory type ...................................................................... nb/intel/ironlake: Specify supported memory type Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71584 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index a614058..678e73a 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -8,6 +8,11 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select NO_DDR2 + select USE_DDR3 if NORTHBRIDGE_INTEL_IRONLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/71584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Gerrit-Change-Number: 71584 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/haswell: Specify supported memory type
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71583 ) Change subject: nb/intel/haswell: Specify supported memory type ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71583/comment/b1cc244b_ffd94006 PS4, Line 12: Note: DDR4 is not supported in coreboot yet for current northbridge. > This line seems to be unchanged. Another idea: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Gerrit-Change-Number: 71583 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 07:22:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/googmb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable ...
by Martin L Roth (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Jason Nien, Chris Wang, Martin Roth. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71647 ) Change subject: mb/googmb/google/skyrim/var/winterhold: enable dxio_tx_vboost_enable for PCIe optimization ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71647/comment/ce606790_2d82668a PS2, Line 6: > Possible long commit subject (prefer a maximum 65 characters) Please fix. https://review.coreboot.org/c/coreboot/+/71647/comment/521fded3_e605faf8 PS2, Line 7: mb/goog remove? -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 07:17:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads: Update GRUB2 stable version from 2.04 to 2.06
by Elyes Haouas (Code Review) 04 Jan '23

04 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55343 ) Change subject: payloads: Update GRUB2 stable version from 2.04 to 2.06 ...................................................................... payloads: Update GRUB2 stable version from 2.04 to 2.06 GRUB2 was released on June 8th, 2021 [1]. [1]: https://lists.gnu.org/archive/html/grub-devel/2021-06/msg00022.html Change-Id: I050a78c769c3cd4c9ae627c7e3124a4894a018d7 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M payloads/external/GRUB2/Kconfig M payloads/external/GRUB2/Makefile 2 files changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index 67499c6..e41c562 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -15,7 +15,7 @@ default GRUB2_STABLE config GRUB2_STABLE - bool "2.04" + bool "2.06" help Stable GRUB2 version diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 5e82f3e..1691e9b 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -1,9 +1,9 @@ TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) -TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04 +TAG-$(CONFIG_GRUB2_STABLE)=grub-2.06 NAME-$(CONFIG_GRUB2_MASTER)=HEAD NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) -NAME-$(CONFIG_GRUB2_STABLE)=2.04 +NAME-$(CONFIG_GRUB2_STABLE)=2.06 project_git_repo=https://git.savannah.gnu.org/git/grub.git/ project_dir=grub2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I050a78c769c3cd4c9ae627c7e3124a4894a018d7 Gerrit-Change-Number: 55343 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hackware <human(a)hackware.cl> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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coreboot-gerrit January 2023