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Change subject: soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro
......................................................................
soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro
Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU
capabilities flags using cpuid_ext inline function.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 19 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/71646/3
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Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros
......................................................................
arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields
values by macros
Macro definitions are from DMTF System Management BIOS (SMBIOS)
Reference Specification (DSP0134) Chapter 7.5.5.
Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686
Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com>
---
M src/arch/x86/smbios.c
M src/include/smbios.h
2 files changed, 96 insertions(+), 6 deletions(-)
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Change subject: vc/siemens/hwilib/Makefile.inc: Remove a link path to itself
......................................................................
Patch Set 10: Verified-1
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167599):
https://review.coreboot.org/c/coreboot/+/70469/comment/6d18898b_50d32b64
PS10, Line 9: Fix:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This could be posted for upstream as well.
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Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71170/comment/75311bae_7fc48851
PS8, Line 9: Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1.
Please split this up to 72 char per line.
File src/mainboard/google/brya/variants/craask/fw_config.c:
https://review.coreboot.org/c/coreboot/+/71170/comment/77b18d19_6bc52fb4
PS8, Line 87: if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME)))
NVMe pins need to stay enabled when fw_config is unprovisioned, so use:
```
if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME)))
```
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Hello Will Kim, build bot (Jenkins), Tarun Tuli, Subrata Banik, Wonkyu Kim, Kapil Porwal, Sridhar Siricilla, Eric Lai,
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Change subject: soc/intel/common: Untie PRMRR from SGX
......................................................................
soc/intel/common: Untie PRMRR from SGX
PRMRR is used by many Intel SOC features, not just Intel SGX.
As of now SGX and Key Locker are the features that need PRMRR.
Untie it from Intel SGX specific files and move to common cpulib.
Also rename PRMRR size config option. Use the renamed PRMRR size
config option to set the PRMRR size.
TEST=Able to set PRMRR size using config.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/sgx/Kconfig
3 files changed, 85 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/70819/20
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
......................................................................
soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
Add below mentioned functions:
is_sgx_configured_and_supported():
Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
Checks if Key Locker is configured and supported
check_prm_features_enabled():
Checks if any of the features that need PRM are configured
and supported. As of now SGX and Key Locker are the only
features that need PRM.
Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/71569/8
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Change subject: amdfwtool: Change "fall through" to "fallthrough"
......................................................................
Patch Set 1:
(7 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/5e9925ec_15d7f293
PS1, Line 2461: case 0: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/2b9a8e20_8e787145
PS1, Line 2462: case 0xFFFA0000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/5610b3aa_1c66d7e8
PS1, Line 2463: case 0xFFF20000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/1050c2ae_ff588bc6
PS1, Line 2464: case 0xFFE20000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/a8e493f1_2839e675
PS1, Line 2465: case 0xFFC20000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/0303beea_0ece65e1
PS1, Line 2466: case 0xFF820000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167593):
https://review.coreboot.org/c/coreboot/+/71648/comment/03b97e1b_20daf7a2
PS1, Line 2467: case 0xFF020000: /* Fallthrough */
Prefer 'fallthrough;' over fallthrough comment
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