coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: soc/amd/common/psp: Support PSP SMI handler
by ritul guru (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, ritul guru, Marshall Dawson, Matt DeVillier, Paul Menzel, Arthur Heymans, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65523 to look at the new patch set (#16). Change subject: soc/amd/common/psp: Support PSP SMI handler ...................................................................... soc/amd/common/psp: Support PSP SMI handler Enable optional support for registering an SMI handler for PSP SPI flash read/write/erase operation requests. The PSP SMI needs to be configured before the PSP can actually issue SMI after being informed of the SMI trigger info via the SMM_INFO command. See AMD document 55570 revision 3.16 for additional details. The PSP will not trigger SMI until informed via the SMM area buffer that SMM requests are ready to be served. See AMD document 55758 revision 2.00 for additional details. Change-Id: Ie1f4646101b90bc52c492f35fd26e6ca1e496142 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c A src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/include/soc/smi.h 13 files changed, 612 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/65523/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/65523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1f4646101b90bc52c492f35fd26e6ca1e496142 Gerrit-Change-Number: 65523 Gerrit-PatchSet: 16 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: device: Clear lane error status
by Nico Huber (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Wilson Chou, Marc Jones, Jonathan Zhang, Ryback Hung, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Shuming Chu (Shuming). Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 ) Change subject: device: Clear lane error status ...................................................................... Patch Set 3: (6 comments) Patchset: PS2: > We need to clear lane error status after (last) link training triggered by coreboot. […] Thanks. Could we make it part of pciexp_retrain_link() then? File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/67264/comment/39a03b74_7c0a83db PS2, Line 546: if (reg32 != 0) { You can avoid the indentation with early returns, e.g. ``` pos = ... if (pos == 0) return; reg32 = ... if (reg32 == 0) return; ``` https://review.coreboot.org/c/coreboot/+/67264/comment/a564db0a_11dfbea9 PS2, Line 548: int bus_num, device_num; : bus_num = dev->bus->secondary; : device_num = dev->path.pci.devfn; : printk(BIOS_DEBUG, "bus = 0x%x dev = 0x%x\n", bus_num, device_num); Please use dev_path(). https://review.coreboot.org/c/coreboot/+/67264/comment/b6258a80_2bb8d4c0 PS2, Line 552: printk(BIOS_DEBUG, "pciexp_find_extended_cap = 0x%x\n", pos); This is probably something to put inside pciexp_find_extended_cap(), if we want to keep it. File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/67264/comment/628c64fa_c6cb0a38 PS2, Line 104: #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ This is (as the comment above says) an offset in type 1 configuration headers. It only shares the number by coincidence. https://review.coreboot.org/c/coreboot/+/67264/comment/a2651f3b_b866d1d3 PS2, Line 465: #define PCI_EXT_CAP_ID_VNDR 0x0b Please add a new define here. See /usr/include/pci/header.h for reference. The offsets within the capability should have there own block below. -- To view, visit https://review.coreboot.org/c/coreboot/+/67264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5 Gerrit-Change-Number: 67264 Gerrit-PatchSet: 3 Gerrit-Owner: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 11:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/kinox: Update the DPTF parameters and fan table
by Sumeet R Pawnikar (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak, Ricky Chang. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67314 ) Change subject: mb/google/brya/var/kinox: Update the DPTF parameters and fan table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67314/comment/fe5a1eb7_c5bbd1d5 PS2, Line 160: 97 Any reason for these Critical temperature values change ? Did you observe that system is hitting the previous value 93C and system getting shutdown ? -- To view, visit https://review.coreboot.org/c/coreboot/+/67314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e Gerrit-Change-Number: 67314 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 10:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/kinox: Update the DPTF parameters and fan table
by Dtrain Hsu (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67314 ) Change subject: mb/google/brya/var/kinox: Update the DPTF parameters and fan table ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Sumeet, Would you help to review? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/67314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e Gerrit-Change-Number: 67314 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 09:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Dtrain Hsu (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67307 ) Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Sumeet and Tim, Would you help to review? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 09:21:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/kinox: Update the DPTF parameters and fan table
by Dtrain Hsu (Code Review) 02 Sep '22

02 Sep '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67314 ) Change subject: mb/google/brya/var/kinox: Update the DPTF parameters and fan table ...................................................................... mb/google/brya/var/kinox: Update the DPTF parameters and fan table Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters and fan table. 1. Modify CRT of TSR0 - TSR3 to 97. 2. Modify TCC offset to 6. 3. Update new fan table. BUG=b:244657172 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 65 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/67314/1 diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index a874b1d..8356320 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -69,6 +69,8 @@ .tdp_pl1_override = 30, }" + register "tcc_offset" = "6" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -82,68 +84,63 @@ ## Active Policy register "policies.active" = "{ [0] = { - .target = DPTF_CPU, + .target = DPTF_TEMP_SENSOR_0, .thresholds = { - TEMP_PCT(80, 97), - TEMP_PCT(65, 93), - TEMP_PCT(58, 86), - TEMP_PCT(50, 80), - TEMP_PCT(45, 64), - TEMP_PCT(43, 52), - TEMP_PCT(40, 47), + TEMP_PCT(90, 97), + TEMP_PCT(60, 80), + TEMP_PCT(55, 70), + TEMP_PCT(50, 64), + TEMP_PCT(45, 54), + TEMP_PCT(42, 47), + TEMP_PCT(38, 43), TEMP_PCT(35, 40), + TEMP_PCT(33, 36), + TEMP_PCT(30, 32), } }, [1] = { - .target = DPTF_TEMP_SENSOR_0, + .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(75, 97), - TEMP_PCT(70, 93), - TEMP_PCT(60, 86), - TEMP_PCT(52, 80), - TEMP_PCT(47, 64), - TEMP_PCT(43, 52), - TEMP_PCT(40, 47), + TEMP_PCT(90, 97), + TEMP_PCT(60, 80), + TEMP_PCT(55, 70), + TEMP_PCT(50, 64), + TEMP_PCT(45, 54), + TEMP_PCT(42, 47), + TEMP_PCT(38, 43), TEMP_PCT(35, 40), + TEMP_PCT(33, 36), + TEMP_PCT(30, 32), } }, [2] = { - .target = DPTF_TEMP_SENSOR_1, + .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(75, 97), - TEMP_PCT(70, 93), - TEMP_PCT(60, 86), - TEMP_PCT(52, 80), - TEMP_PCT(47, 64), - TEMP_PCT(43, 52), - TEMP_PCT(40, 47), + TEMP_PCT(90, 97), + TEMP_PCT(60, 80), + TEMP_PCT(55, 70), + TEMP_PCT(50, 64), + TEMP_PCT(45, 54), + TEMP_PCT(42, 47), + TEMP_PCT(38, 43), TEMP_PCT(35, 40), + TEMP_PCT(33, 36), + TEMP_PCT(30, 32), } }, [3] = { - .target = DPTF_TEMP_SENSOR_2, - .thresholds = { - TEMP_PCT(75, 97), - TEMP_PCT(70, 93), - TEMP_PCT(60, 86), - TEMP_PCT(52, 80), - TEMP_PCT(47, 64), - TEMP_PCT(43, 52), - TEMP_PCT(40, 47), - TEMP_PCT(35, 40), - } - }, - [4] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(75, 97), - TEMP_PCT(70, 93), - TEMP_PCT(60, 86), - TEMP_PCT(52, 80), - TEMP_PCT(47, 64), - TEMP_PCT(43, 52), - TEMP_PCT(40, 47), + TEMP_PCT(90, 97), + TEMP_PCT(60, 80), + TEMP_PCT(55, 70), + TEMP_PCT(50, 64), + TEMP_PCT(45, 54), + TEMP_PCT(42, 47), + TEMP_PCT(38, 43), TEMP_PCT(35, 40), + TEMP_PCT(33, 36), + TEMP_PCT(30, 32), } } }" @@ -160,10 +157,10 @@ ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 93, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 93, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 93, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 93, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 97, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 97, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 97, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 97, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/67314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e Gerrit-Change-Number: 67314 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add gpio override settings
by EricKY Cheng (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthikeyan Ramasubramanian. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67209 ) Change subject: mb/google/skyrim/var/winterhold: Add gpio override settings ...................................................................... Patch Set 5: (4 comments) File src/mainboard/google/skyrim/variants/winterhold/gpio.c: https://review.coreboot.org/c/coreboot/+/67209/comment/5a6a0ba9_9cf75897 PS4, Line 10: // NC > Remove these extra comments. […] Done https://review.coreboot.org/c/coreboot/+/67209/comment/f50d3504_fbab0b3c PS4, Line 16: SD_AUX_RESET_L > nit: SD_AUX_RST_SOC_L (to match Glacier_Mendocino_FT6_SOC_GPIO_PM&Strap_20220815A) Done https://review.coreboot.org/c/coreboot/+/67209/comment/20fe5549_be399440 PS4, Line 22: /* CLK_REQ1_L / EMMC */ > How about this? The REQ1 is for EMMC on winterhold https://review.coreboot.org/c/coreboot/+/67209/comment/bd7111ed_b15ba639 PS4, Line 25: __weak > You don't want to make this weak Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc Gerrit-Change-Number: 67209 Gerrit-PatchSet: 5 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Sep 2022 07:41:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable DSP UPD
by Subrata Banik (Code Review) 02 Sep '22

02 Sep '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67270 ) Change subject: mb/google/rex: Enable DSP UPD ...................................................................... mb/google/rex: Enable DSP UPD Enable DSP setting. Make sure the SSP can work as expected. BUG=b:243123156 TEST=Dev beep working on Rex. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Ivy Jian: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 3471c7e..1f079e29 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -20,6 +20,11 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + device domain 0 on device ref igpu on end device ref dtt on end -- To view, visit https://review.coreboot.org/c/coreboot/+/67270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132 Gerrit-Change-Number: 67270 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update devicetree setting
by EricKY Cheng (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Nien, Martin Roth. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67308 ) Change subject: mb/google/skyrim/var/winterhold: Update devicetree setting ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/variants/winterhold/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67308/comment/a8bb8706_6226fe69 PS1, Line 146: > trailing whitespace Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/67308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Gerrit-Change-Number: 67308 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 07:01:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update devicetree setting
by build bot (Jenkins) (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Nien, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67308 ) Change subject: mb/google/skyrim/var/winterhold: Update devicetree setting ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/variants/winterhold/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-157943): https://review.coreboot.org/c/coreboot/+/67308/comment/b5d48720_19f2a779 PS1, Line 146: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/67308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Gerrit-Change-Number: 67308 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 06:58:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2022