coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/amd: Throttle SOC during low/no battery
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67189 ) Change subject: soc/amd: Throttle SOC during low/no battery ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/skyrim/variants/skyrim/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67189/comment/a770ef58_6d9b3cf2 PS5, Line 234: # Normal > The Normal values should have existed when `acipgen_dptci()` was added for Mendocino. […] No one is setting `dptc_enable`, so we don't have to worry about writing incorrect data. We should move the skyrim specific CL into it's own CL. This makes reverting easier. I would add all the non-low-battery config in a new CL. That way you can explain where you got the values from, and why they are correct for skyrim. I would then have a different CL that adds the low-battery overrides and also sets `dptc_tablet_mode_enable`. Having the different CLs will make it easier to bisect and blame any regressions. File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/67189/comment/b66a3c8c_d94a00f4 PS7, Line 68: vrm_current_limit_mA Do we need to pass these into FSP as well? https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… If so, let's have a new CL that adds the 3 new parameters. -- To view, visit https://review.coreboot.org/c/coreboot/+/67189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086 Gerrit-Change-Number: 67189 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Add low/no battery mode to DPTC
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66804 ) Change subject: soc/amd: Add low/no battery mode to DPTC ...................................................................... Patch Set 16: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66804/comment/1ff5f333_30331873 PS16, Line 7: soc/amd soc/amd/common/acpi https://review.coreboot.org/c/coreboot/+/66804/comment/071586ea_813d1ee8 PS16, Line 13: refactor CL It's not really a refactor CL, it's adding new functionality. File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/66804/comment/54f34c29_d30739f3 PS16, Line 20: ( Do we need to group these? -- To view, visit https://review.coreboot.org/c/coreboot/+/66804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397 Gerrit-Change-Number: 66804 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdblocks/alib.h: Add DPTC parameter IDs
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67182 ) Change subject: amdblocks/alib.h: Add DPTC parameter IDs ...................................................................... amdblocks/alib.h: Add DPTC parameter IDs Add additional DPTC parameter IDs that are necessary when throttling the SOC due to low/no battery. These additional parameters are used in later CLs. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp(a)google.com> Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67182 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/alib.h 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 61608d5..8899c78 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -14,6 +14,12 @@ ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID = 0x5, ALIB_DPTC_FAST_PPT_LIMIT_ID = 0x6, ALIB_DPTC_SLOW_PPT_LIMIT_ID = 0x7, + ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID = 0x8, + ALIB_DPTC_PROCHOT_L_DEASSERTION_RAMP_TIME_ID = 0x9, + ALIB_DPTC_VRM_CURRENT_LIMIT_ID = 0xb, + ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT = 0xc, + /* Picasso: SetVrmSocCurrentLimit (0xe) is not implemented in alib. */ + ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID = 0xe, }; struct alib_dptc_param { -- To view, visit https://review.coreboot.org/c/coreboot/+/67182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc Gerrit-Change-Number: 67182 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: amdblocks/alib.h: Add DPTC parameter IDs
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Tim Van Patten, Fred Reitberger. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67182 ) Change subject: amdblocks/alib.h: Add DPTC parameter IDs ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc Gerrit-Change-Number: 67182 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:48:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Refactor DPTC Tablet Mode
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

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[M] Change in coreboot[master]: soc/amd: Remove unsupported DPTC tablet mode settings
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67181 ) Change subject: soc/amd: Remove unsupported DPTC tablet mode settings ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > Currently, no tablet mode DPTC values exist for these SOCs in the device tree, so the feature can't be enabled for anything anyway. This removes the possibility of enabling a broken feature. Well you would set the values and set `dptc_enable = true`. So I wouldn't say it's enabling a broken feature, it just needs to be configured. > If this is the case, maybe tablet mode shouldn't be an SOC feature and should be moved into the mainboards for boards that do support it? Well here's the dirty little secret, the `.asl` is looking at Chrome EC specific registers to determine the states. So it really is a Google specific feature right now. We just don't have a good spot for chromeos/amd code that is shared between SoCs. -- To view, visit https://review.coreboot.org/c/coreboot/+/67181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57 Gerrit-Change-Number: 67181 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Refactor DPTC Tablet Mode
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Jason Nien, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66994 ) Change subject: soc/amd: Refactor DPTC Tablet Mode ...................................................................... Patch Set 10: (4 comments) File src/mainboard/google/zork/variants/morphius/overridetree.cb: https://review.coreboot.org/c/coreboot/+/66994/comment/7023cb3d_24dc5e9a PS9, Line 34: true quote File src/soc/amd/cezanne/chip.h: https://review.coreboot.org/c/coreboot/+/66994/comment/a93ee14f_2e7b429f PS10, Line 91: /* Enable dptc tablet mode */ : bool dptc_tablet_mode_enable; Hrmm, how about you reorder your Cls. Move the CL that deletes the tablet mode before this one. File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/66994/comment/066bb799_5869d956 PS10, Line 120: /* Enable dptc for tablet mode */ : bool dptc_enable; So in reality this bit is already doing what you want. Maybe just rename it to `dptc_tablet_mode_enable`? Then in `acipgen_dptci` you can check `if (!dptc_tablet_mode_enable && !dptc_low_battery_enable)`. I don't think we need a global bit to enable dptci. Just all the individual states. File src/soc/amd/picasso/root_complex.c: https://review.coreboot.org/c/coreboot/+/66994/comment/902fe93b_9f65c4b2 PS4, Line 201: thermctl_limit_tablet_mode_degreeC > Are you referring to defining a structure that matches the DPTC parameters defined in the `DPTC_INPU […] I was suggesting moving all the config parameters into a common struct. We currently have `struct soc_amd_common_config common_config;`, so maybe add a new `struct soc_amd_common_thermal_config`. It can contain all the `fast_ppt_limit_mW`, `fast_ppt_limit_tablet_mode_mW`, etc. We could always move the `DPTC_INPUTS` macro into the `chip.h`. Then this code simply reads the `struct dptc_input` from the soc `chip` config. I agree we can do more refactoring in a follow up though. -- To view, visit https://review.coreboot.org/c/coreboot/+/66994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Gerrit-Change-Number: 66994 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:42:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amd: Convert dptc_enable to bool
by Raul Rangel (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Paul Menzel, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67188 ) Change subject: amd: Convert dptc_enable to bool ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/zork/variants/morphius/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67188/comment/11e4d870_39116cb0 PS5, Line 33: true > > Why do we quote all the simple fields then!? […] I would say quote it to keep the consistency. If we want to change styles, let's do them all at once to avoid any confusion going forward. -- To view, visit https://review.coreboot.org/c/coreboot/+/67188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5 Gerrit-Change-Number: 67188 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:31:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: lib/xxhash.c: Add new hash functions
by Fred Reitberger (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Julius Werner. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67300 ) Change subject: lib/xxhash.c: Add new hash functions ...................................................................... Patch Set 2: (3 comments) File src/lib/xxhash.c: https://review.coreboot.org/c/coreboot/+/67300/comment/428a1b4d_2b879e10 PS1, Line 7: * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) > Don't need the full text here, that's what the SPDX tag is for. Wasn't sure of the etiquette here. Trimmed the license text. https://review.coreboot.org/c/coreboot/+/67300/comment/39f0b83d_c3fa16b6 PS1, Line 57: #endif > unused? Done https://review.coreboot.org/c/coreboot/+/67300/comment/2d8e8976_10155192 PS1, Line 90: if (IS_ALIGNED(up, 4)) { > I don't think you want to do this, it's gonna kill your performance. […] Yeah, the kernel has <asm/unaligned.h> to handle all of these cases. I wasn't sure if there were any coreboot platforms that did not support an efficient unaligned access, so tried to make something work here. Assuming all platforms support unaligned access simplifies this. If that ever changes in the future, then it would probably be good to abstract that into something similar to <asm/unaligned.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/67300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c Gerrit-Change-Number: 67300 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Sep 2022 17:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: lib/xxhash.c: Add new hash functions
by Fred Reitberger (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Fred Reitberger. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67300 to look at the new patch set (#2). Change subject: lib/xxhash.c: Add new hash functions ...................................................................... lib/xxhash.c: Add new hash functions Add xxhash functions. This is a very fast hash function, running at RAM speed limits. This code was adapted from the linux kernel with minor modifications to make it fit in coreboot. BUG=b:193557430 TEST=compile Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c --- A src/include/xxhash.h M src/lib/Makefile.inc A src/lib/xxhash.c 3 files changed, 721 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/67300/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c Gerrit-Change-Number: 67300 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2022