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Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout
......................................................................
util/amdfwtool/amdfwread: Handle recovery A/B layout
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to
handle it.
Also add a generic read_header function to read different header types.
BUG=None
TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to
dump the Softfuse entry.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15
---
M util/amdfwtool/amdfwread.c
1 file changed, 77 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/66554/7
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Change subject: util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
......................................................................
util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
Optional arguments that involve printing information from the firmware
image is mapped to bit fields with bit 31 set. But instead of just
setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask.
BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48
---
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/66573/6
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Change subject: util/amdfwtool/amdfwread: Update relative_offset function
......................................................................
util/amdfwtool/amdfwread: Update relative_offset function
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables
Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.
BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.
Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M util/amdfwtool/amdfwread.c
1 file changed, 38 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/66572/6
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67239 )
Change subject: cpu/x86/lapic.h: Fix CONFIG_X2APIC_RUNTIME
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67239/comment/2f91cb25_10cae370
PS1, Line 10: the cpu is in x2apic mode.
> > Are you sure it deadlocks without this? There is some discussion about the lack or serializations […]
CB:60213 tries to explain the X2APIC_ONLY case.
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Change subject: util/docker/coreboot-jenkins-node: Install cmocka
......................................................................
Patch Set 4: Code-Review+2
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Change subject: util/docker/coreboot-jenkins-node: Install cmocka
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> It seems a little odd, all the other flashrom dependencies are also in coreboot-sdk. […]
Removed coreboot from the commit message.
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Change subject: util/docker/coreboot-jenkins-node: Install cmocka
......................................................................
util/docker/coreboot-jenkins-node: Install cmocka
flashrom uses cmocka for unit testing. Install it so that the CI can
use it.
Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b
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Change subject: skyrim/overridetree: Enable DPTC and No Battery Mode
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/skyrim/variants/skyrim/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67211/comment/435ea537_de844919
PS3, Line 261: # Throttle (e.g., Low/No Battery)
: register "vrm_current_limit_throttle_mA" = "20000"
: register "vrm_maximum_current_limit_throttle_mA" = "20000"
: register "vrm_soc_current_limit_throttle_mA" = "10000"
I would set the values in this CL since it's the CL that enables the feature.
Maybe move the `register "dptc_no_battery_mode_enable" = true` right below the `# Throttle` comment so it's obvious that bit is guarding these fields.
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