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Change subject: soc/amd: Refactor DPTC Tablet Mode
......................................................................
Patch Set 10:
(1 comment)
File src/soc/amd/common/acpi/dptc.asl:
https://review.coreboot.org/c/coreboot/+/66994/comment/48274aea_12a4b2c6
PS9, Line 15:
> I don't quite understand the question. The flow is: […]
Ack. Yes that is what I was looking for.
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Change subject: soc/amd: Refactor DPTC Tablet Mode
......................................................................
Patch Set 10:
(3 comments)
File src/soc/amd/common/acpi/dptc.asl:
https://review.coreboot.org/c/coreboot/+/66994/comment/6a5fce5e_efa02daa
PS9, Line 15:
> I understand this as DPTC tablet mode. Otherwise DPTC Default. […]
I don't quite understand the question. The flow is:
- If the method `_SB.DDEF()` doesn't exist, then DPTC is not enabled so return immediatley.
- If the method `_SB.DTAB()` exists and the device is in tablet mode (`TBMD == One`), then enable the tablet mode DPTC settings and return.
- Enable the default DPTC settings via `_SB.DDEF()` (done during boot or when the device goes from tablet mode -> laptop mode).
Is that what you're looking for?
File src/soc/amd/common/block/acpi/alib.c:
https://review.coreboot.org/c/coreboot/+/66994/comment/95320b22_473782b7
PS9, Line 43: acpigen_pop_len(); /* Method DDEF */
> acpigen_write_method_end();
Done
https://review.coreboot.org/c/coreboot/+/66994/comment/85ceccfa_bf44ae6b
PS9, Line 45: acpigen_pop_len(); /* Scope \_SB */
> acpigen_write_scope_end(); […]
Done
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Change subject: amd: Convert dptc_enable to bool
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/zork/variants/morphius/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67188/comment/af6ff4c0_720c7073
PS5, Line 33: true
> Why do we quote all the simple fields then!?
At least we know it's unnecessary, so we can get rid of some of the clutter going forward.
Do I need to add them to get the CR+2 or are we ok with this version?
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/66804
to look at the new patch set (#16).
Change subject: soc/amd: Add low/no battery mode to DPTC
......................................................................
soc/amd: Add low/no battery mode to DPTC
Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.
This refactor CL is in preparation for enabling this functionality for
the Mendocino SOC.
BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp(a)google.com>
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
---
M src/soc/amd/common/acpi/dptc.asl
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
3 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/66804/16
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Refactor DPTC Tablet Mode
......................................................................
soc/amd: Refactor DPTC Tablet Mode
Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.
1. Refactor and simplify acpigen_write_alib_dptc() into the following
functions:
- acpigen_write_alib_dptc_default()
- acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enabled to control
whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
the DPTC settings.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim
Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp(a)google.com>
---
M src/mainboard/google/zork/variants/morphius/overridetree.cb
M src/soc/amd/cezanne/acpi/soc.asl
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/root_complex.c
A src/soc/amd/common/acpi/dptc.asl
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/acpi/soc.asl
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/root_complex.c
M src/soc/amd/picasso/acpi/soc.asl
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/root_complex.c
14 files changed, 162 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/66994/10
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Change subject: amd: Convert dptc_enable to bool
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/zork/variants/morphius/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67188/comment/091d753d_300a431e
PS5, Line 33: true
> No, it doesn't need to be quoted. These values work correctly as raw `true`/`false` without quotes. […]
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
Would you look at that.... apparently any non space character is considered a STRING... Why do we quote all the simple fields then!?
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Change subject: amd: Convert dptc_enable to bool
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/zork/variants/morphius/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67188/comment/302ce9e7_5bc3d103
PS5, Line 33: true
> You need to quote this don't you?
No, it doesn't need to be quoted. These values work correctly as raw `true`/`false` without quotes.
Specifically, I've verified that `true` outputs the necessary methods, while they are not present with `false` (no quotes on either):
`SSDT1.dsl`
```
Scope (\_SB)
{
Method (DDEF, 0, Serialized)
{
Debug = "DPTC: Using normal SOC DPTC Settings."
Name (DEFB, Buffer (0x25)
{
...
})
\_SB.ALIB
0x0C
DEFB
}
}
Scope (\_SB)
{
Method (DTHL, 0, Serialized)
{
Debug = "DPTC: Using low/no battery mode SOC DPTC settings."
Name (THTL, Buffer (0x25)
{
...
})
\_SB.ALIB
0x0C
THTL
}
}
```
If it's just for consistency's sake, I can add them, but it doesn't appear to be necessary.
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Change subject: util/docker/coreboot-jenkins-node: Install cmocka
......................................................................
Patch Set 2:
(1 comment)
File util/docker/coreboot-jenkins-node/Dockerfile:
https://review.coreboot.org/c/coreboot/+/67272/comment/9f192a05_393a5ade
PS2, Line 27: libcmocka-dev \
Nit: The list is in a alphabetic order.
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67179 )
Change subject: util/docker/coreboot-sdk: Install cmocka
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Patch Set 2:
(1 comment)
Patchset:
PS2:
> Nothing afaik. […]
Some compiling error late in the build. Had nothing to do with the change, but I had no time for a deeper look.
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67301 )
Change subject: soc/amd/common/block/apob: Add hashed APOB support
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Patch Set 3:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/67301/comment/3afe3057_f0228c17
PS2, Line 22: RW_MRC_HASH
> SPI is random access, so you can call `rdev_readat` with what ever offset you want. […]
Okay, I'll give that a test and see if I can simplify this even more.
I don't have older hardware, so I have no way to test cezanne/zork, but they should be able to support this as long as there are 8 bytes free at the end of the MRC_CACHE block. My plan was to enable it first on chausie/skyrim and then opt-in other boards from there.
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