coreboot-gerrit September 2022

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update devicetree setting
by EricKY Cheng (Code Review) 02 Sep '22

02 Sep '22

EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67308 ) Change subject: mb/google/skyrim/var/winterhold: Update devicetree setting ...................................................................... mb/google/skyrim/var/winterhold: Update devicetree setting Initialize winterhold devicetree. BUG=b:241196632 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 190 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/67308/1 diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 7a56f93..2857a02 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -1,5 +1,179 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/mendocino - device domain 0 on end + device domain 0 on + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref xhci_1 on # XHCI1 controller + chip drivers/usb/acpi + device ref xhci_1_root_hub on # XHCI1 root hub + chip drivers/usb/acpi + device ref usb3_port3 on # USB 3.1 port3 + chip drivers/usb/hub + register "desc" = ""USB Hub"" + register "name" = ""VL822"" + register "port_count" = "4" + device usb 0.0 on # VL822 USB3 hub + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(2, 2)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_42)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_8)" + register "enable_delay_ms" = "20" + device usb 3.1 on end + end + end # VL822 USB3 hub + end + end # USB 3.1 port3 + end + chip drivers/usb/acpi + device ref usb2_port3 on # USB 2 port3 + chip drivers/usb/hub + register "desc" = ""USB Hub"" + register "name" = ""VL822"" + register "port_count" = "4" + device usb 0.0 on # VL822 USB2 hub + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + end # VL822 USB2 hub + end + end # USB 2 port3 + end + end # XHCI1 root hub + end + end # XHCI1 controller + end # Internal GPP Bridge 0 to Bus A + end # domain + + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "wake" = "GEVENT_20" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7863"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_40)" + register "generic.wake" = "GEVENT_20" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C0 + device ref i2c_1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_off_delay_ms" = "1" + register "generic.reset_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_delay_ms" = "180" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_3)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end + end # I2C1 + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "2" + register "probed" = "1" + device i2c 2a on end + end + end # I2C2 + + device ref uart_1 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "wake" = "GEVENT_15" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "enable_delay_ms" = "3" + device generic 0 alias fpmcu on end + end + end # UART1 + end # chip soc/amd/mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/67308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Gerrit-Change-Number: 67308 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Subrata Banik (Code Review) 02 Sep '22

02 Sep '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling Enabling Bus Master isn't required by the hardware, so we shouldn't need to enable it at all. However, some payloads do not set this bit before attempting DMA transfers, which results in functionality failure. For example: in this case, unable to see the developer screen in Depthcharge. In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for the IGD BAR resources but starting with the MTL platform, it fails to do so resulting into inability to see the Pre-OS display. BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX PEIM Display Init is successful during AP boot) TEST=Able to see the developer screen with eDP/HDMI while booting the Google/Rex. Also, this change doesn't impact the previous platforms (ADL, TGL, CML etc.) where the BM is default enabled. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e4ef458..6b5770c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -180,6 +180,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_init, + .final = pci_dev_request_bus_master, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = gma_generate_ssdt, -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: qualcomm/sc7280: remove malloc allocation for tu and add early return...
by Yu-Ping Wu (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Shelley Chen, Venkat Thogaru, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66975 ) Change subject: qualcomm/sc7280: remove malloc allocation for tu and add early return for failure case ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66975/comment/d1d8147a_f29ad42a PS2, Line 6: > Possible long commit subject (prefer a maximum 65 characters) Please fix. How about `remove unnecessary malloc and early return on failure` https://review.coreboot.org/c/coreboot/+/66975/comment/84f218b9_9d8ee5c9 PS2, Line 9: priniting printing https://review.coreboot.org/c/coreboot/+/66975/comment/5522f700_63f3b5c8 PS2, Line 11: static It's not a static variable, just a local variable. File src/soc/qualcomm/sc7280/display/edp_ctrl.c: https://review.coreboot.org/c/coreboot/+/66975/comment/d71c0179_6492a7b4 PS2, Line 1225: tu_table Align with BIOS_INFO. -- To view, visit https://review.coreboot.org/c/coreboot/+/66975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Gerrit-Change-Number: 66975 Gerrit-PatchSet: 2 Gerrit-Owner: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Sep 2022 03:19:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Dtrain Hsu (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67307 to look at the new patch set (#2). Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... mb/google/brya/var/kinox: Modify fan speed/duty table Modify fan speed/duty table follow "Duty table.xlsx". The table has 20 elements so sets the DPTF_MAX_FAN_PERF_STATES from 10 to 20. BUG=b:244262869 TEST=Boot to ChromeOS. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 --- M src/include/acpi/acpigen_dptf.h M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 37 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/67307/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Dtrain Hsu (Code Review) 02 Sep '22

02 Sep '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67307 ) Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... mb/google/brya/var/kinox: Modify fan speed/duty table Modify fan speed/duty table follow "Duty table.xlsx". The table has 20 elements so sets the DPTF_MAX_FAN_PERF_STATES from 10 to 20. BUG=b:244262869 TEST=Boot to Chrome OS. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 --- M src/include/acpi/acpigen_dptf.h M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 37 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/67307/1 diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 893256e..6ef87a4 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -41,7 +41,7 @@ /* Maximum found by automatic inspection (awk) */ DPTF_MAX_CHARGER_PERF_STATES = 10, - DPTF_MAX_FAN_PERF_STATES = 10, + DPTF_MAX_FAN_PERF_STATES = 20, /* From ACPI spec 6.3 */ DPTF_FIELD_UNUSED = 0xFFFFFFFFull, diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 95eba1f..a874b1d 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -196,16 +196,26 @@ }" ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } + [0] = { 100, 6060, 0, 0, }, + [1] = { 90, 5585, 0, 0, }, + [2] = { 80, 4964, 0, 0, }, + [3] = { 70, 4237, 0, 0, }, + [4] = { 64, 3963, 0, 0, }, + [5] = { 60, 3510, 0, 0, }, + [6] = { 54, 3212, 0, 0, }, + [7] = { 50, 2808, 0, 0, }, + [8] = { 48, 2776, 0, 0, }, + [9] = { 47, 2715, 0, 0, }, + [10] = { 45, 2566, 0, 0, }, + [11] = { 43, 2415, 0, 0, }, + [12] = { 40, 2010, 0, 0, }, + [13] = { 36, 1813, 0, 0, }, + [14] = { 35, 1686, 0, 0, }, + [15] = { 32, 1404, 0, 0, }, + [16] = { 30, 1160, 0, 0, }, + [17] = { 20, 760, 0, 0, }, + [18] = { 10, 760, 0, 0, }, + [19] = { 0, 0, 0, 0, } }" ## Fan options -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cbfs/vboot: Adapt to new vb2_digest API
by Yu-Ping Wu (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Erik van den Bogaert, Jakub Czapiga, Frans Hendriks, Tim Wawrzynczak, Christian Walter, Julius Werner, Kangheui Won. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66561 ) Change subject: cbfs/vboot: Adapt to new vb2_digest API ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Gerrit-Change-Number: 66561 Gerrit-PatchSet: 8 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 02:39:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Kapil Porwal (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Subrata Banik, Ivy Jian, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Raj Astekar. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 01:46:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbfs/vboot: Adapt to new vb2_digest API
by Julius Werner (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Erik van den Bogaert, Jakub Czapiga, Frans Hendriks, Tim Wawrzynczak, Christian Walter, Julius Werner, Kangheui Won. Hello Erik van den Bogaert, build bot (Jenkins), Frans Hendriks, Jakub Czapiga, Kangheui Won, Tim Wawrzynczak, Christian Walter, Yu-Ping Wu, Kangheui Won, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66561 to look at the new patch set (#8). Change subject: cbfs/vboot: Adapt to new vb2_digest API ...................................................................... cbfs/vboot: Adapt to new vb2_digest API CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e --- M 3rdparty/vboot M payloads/libpayload/include/cbfs_glue.h M payloads/libpayload/libcbfs/cbfs.c M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/include/cbfs_glue.h M src/lib/cbfs.c M src/lib/metadata_hash.c M src/security/tpm/tspi/tspi.c M src/security/vboot/misc.h M src/security/vboot/mrc_cache_hash_tpm.c M src/security/vboot/tpm_common.c M src/soc/intel/alderlake/hsphy.c M src/soc/intel/common/block/cse/cse_lite.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M tests/lib/cbfs-verification-test.c M util/cbfstool/cbfs_glue.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c M util/cbfstool/platform_fixups.c 21 files changed, 124 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/66561/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/66561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Gerrit-Change-Number: 66561 Gerrit-PatchSet: 8 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: device: Clear lane error status
by Wilson Chou (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Marc Jones, Nico Huber, Ryback Hung, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Shuming Chu (Shuming). Wilson Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 ) Change subject: device: Clear lane error status ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67264/comment/9742ce70_2355b4f8 PS2, Line 2: Author: WilsonChou3333 <Wilson.Chou(a)quantatw.com> > git config --global user.name "Wilson Chou" […] Done https://review.coreboot.org/c/coreboot/+/67264/comment/e8c6107b_4ee9fd3e PS2, Line 7: src/ > `src/` is not needed. Done https://review.coreboot.org/c/coreboot/+/67264/comment/d07f2cc3_694e157c PS2, Line 11: , to > Maybe end the sentence with a dot/period, and start a new one. Done https://review.coreboot.org/c/coreboot/+/67264/comment/2e539fb0_f55333f7 PS2, Line 12: clear > clears Done https://review.coreboot.org/c/coreboot/+/67264/comment/16d5fc75_d07f325a PS2, Line 13: reqgister > register Done https://review.coreboot.org/c/coreboot/+/67264/comment/e825afe5_29303911 PS2, Line 21: > What was shown before? It happens randomly. If it records an error, it will show Capabilities: [a30 v1] Secondary PCI Express LnkCtl3: LnkEquIntrruptEn- PerformEqu- LaneErrStat: LaneErr at lane: 5 https://review.coreboot.org/c/coreboot/+/67264/comment/a5e39130_9ed4e078 PS2, Line 22: WilsonChou3333 > Wilson Chou Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5 Gerrit-Change-Number: 67264 Gerrit-PatchSet: 3 Gerrit-Owner: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Sep 2022 01:03:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbfs/vboot: Adapt to new vb2_digest API
by Julius Werner (Code Review) 02 Sep '22

02 Sep '22

Attention is currently required from: Erik van den Bogaert, Jakub Czapiga, Frans Hendriks, Tim Wawrzynczak, Christian Walter, Julius Werner, Kangheui Won. Hello Erik van den Bogaert, build bot (Jenkins), Frans Hendriks, Jakub Czapiga, Kangheui Won, Tim Wawrzynczak, Christian Walter, Yu-Ping Wu, Kangheui Won, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66561 to look at the new patch set (#7). Change subject: cbfs/vboot: Adapt to new vb2_digest API ...................................................................... cbfs/vboot: Adapt to new vb2_digest API CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e --- M 3rdparty/vboot M payloads/libpayload/include/cbfs_glue.h M payloads/libpayload/libcbfs/cbfs.c M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/include/cbfs_glue.h M src/lib/cbfs.c M src/lib/metadata_hash.c M src/security/tpm/tspi/tspi.c M src/security/vboot/misc.h M src/security/vboot/mrc_cache_hash_tpm.c M src/security/vboot/tpm_common.c M src/soc/intel/alderlake/hsphy.c M src/soc/intel/common/block/cse/cse_lite.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M tests/lib/cbfs-verification-test.c M util/cbfstool/cbfs_glue.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c M util/cbfstool/platform_fixups.c 21 files changed, 121 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/66561/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/66561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Gerrit-Change-Number: 66561 Gerrit-PatchSet: 7 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2022