coreboot-gerrit September 2022

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[M] Change in coreboot[master]: Documentation: Add some more acronyms to the list.
by Martin L Roth (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67330 to look at the new patch set (#2). Change subject: Documentation: Add some more acronyms to the list. ...................................................................... Documentation: Add some more acronyms to the list. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d --- M Documentation/acronyms.md 1 file changed, 55 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/67330/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Gerrit-Change-Number: 67330 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: allocator_v4: Treat above 4G resources more natively
by Nico Huber (Code Review) 05 Sep '22

05 Sep '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65413 ) Change subject: allocator_v4: Treat above 4G resources more natively ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: > Was there some sign that I missed? I didn't see it marked as WIP, and it looked like all of the pat […] No sign, the tree is just in a worse state than we hoped for. -- To view, visit https://review.coreboot.org/c/coreboot/+/65413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Gerrit-Change-Number: 65413 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 16:51:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI
by Angel Pons (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Bill XIE, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67089 ) Change subject: mb/hp/z220_series: Add configs for integrated XHCI ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67089/comment/90739489_822a1404 PS8, Line 13: for a variant. Needs an update. -- To view, visit https://review.coreboot.org/c/coreboot/+/67089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Gerrit-Change-Number: 67089 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 05 Sep 2022 16:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI
by Angel Pons (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Bill XIE, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67089 ) Change subject: mb/hp/z220_series: Add configs for integrated XHCI ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67089/comment/16f57c55_b0002f9a PS6, Line 9: register "xhci_overcurrent_mapping" = "0x0000000f" > Now I move "xhci_overcurrent_mapping" back to devicetree.cb with value "0x0000000f". Given that both variants have the same USB overcurrent mapping (early_init.c is shared), it's reasonable to assume that they have the same xHCI overcurrent mapping. -- To view, visit https://review.coreboot.org/c/coreboot/+/67089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Gerrit-Change-Number: 67089 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 05 Sep 2022 16:49:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/lint: Add rules.h & compiler.h to 019-header-files linter
by Martin L Roth (Code Review) 05 Sep '22

05 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67350 ) Change subject: util/lint: Add rules.h & compiler.h to 019-header-files linter ...................................................................... util/lint: Add rules.h & compiler.h to 019-header-files linter The rules.h & compiler.h includes were removed in previous commits, so add the checks to keep them out to the linter. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d --- M util/lint/lint-stable-019-header-files 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/67350/1 diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files index c839dc5..6adf6c5 100755 --- a/util/lint/lint-stable-019-header-files +++ b/util/lint/lint-stable-019-header-files @@ -9,8 +9,7 @@ INCLUDED_DIRS='^src/' EXCLUDED_FILES='src/include/kconfig.h' -# TODO: Add rules when those patches are complete -HEADER_FILES="k*config" +HEADER_FILES="k?config rules compiler" # Use git grep if the code is in a git repo, otherwise use grep. if [ -n "$(command -v git)" ] && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/67350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Gerrit-Change-Number: 67350 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/soc/intel: remove force-included header compiler.h from file
by Martin L Roth (Code Review) 05 Sep '22

05 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67349 ) Change subject: src/soc/intel: remove force-included header compiler.h from file ...................................................................... src/soc/intel: remove force-included header compiler.h from file The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 --- M src/soc/intel/common/block/scs/early_mmc.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/67349/1 diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index caee7d9..4e76533 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -5,7 +5,6 @@ #include <commonlib/storage/sd_mmc.h> #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> -#include <compiler.h> #include <console/console.h> #include <device/pci.h> #include <intelblocks/mmc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/67349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Gerrit-Change-Number: 67349 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src: remove force-included header rules.h from individual files
by Martin L Roth (Code Review) 05 Sep '22

05 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67348 ) Change subject: src: remove force-included header rules.h from individual files ...................................................................... src: remove force-included header rules.h from individual files The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db --- M src/arch/arm/armv7/cpu.S M src/arch/arm/include/arch/header.ld M src/arch/arm64/include/arch/header.ld M src/arch/riscv/include/arch/header.ld M src/arch/x86/assembly_entry.S M src/arch/x86/include/arch/header.ld M src/include/cbfs_glue.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/nvidia/tegra210/memlayout.ld 9 files changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/67348/1 diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index bc3ebd9..3459fc6 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -6,7 +6,6 @@ */ #include <arch/asm.h> -#include <rules.h> /* * Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0] diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld index cb69ba3..b1e1f9d 100644 --- a/src/arch/arm/include/arch/header.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index 4f37176..c6d48e7 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index d814772..ddb618c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(riscv) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 6e73027..79d6e19 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 4e78ae7..5b380fa 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <rules.h> - PHDRS { to_load PT_LOAD; diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h index 652cf1b..d4fe367 100644 --- a/src/include/cbfs_glue.h +++ b/src/include/cbfs_glue.h @@ -6,7 +6,6 @@ #include <commonlib/region.h> #include <console/console.h> #include <security/vboot/misc.h> -#include <rules.h> /* * This flag prevents linking hashing functions into stages where they're not required. We don't diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 1c905a4..552ba15 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#include <rules.h> #include <intelblocks/msr.h> .section .init, "ax", @progbits diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 42f2164..d9d7070 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <memlayout.h> -#include <rules.h> #include <arch/header.ld> -- To view, visit https://review.coreboot.org/c/coreboot/+/67348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Gerrit-Change-Number: 67348 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/lint/checkpatch: check for phases in commit message.
by Martin L Roth (Code Review) 05 Sep '22

05 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67347 ) Change subject: util/lint/checkpatch: check for phases in commit message. ...................................................................... util/lint/checkpatch: check for phases in commit message. The phase names shouldn't be used in the commit message, so add a gentle reminder in checkpatch. This can be ignored so if it's not needed, no harm done. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ia0fe7c75cc10926a3f4713c350c39af11b62bbae --- M util/lint/checkpatch.pl 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/67347/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 650ddff..5f17aeb 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -2938,6 +2938,14 @@ } } +# coreboot: Check for project phase names in commit message +# Phase names should generally not be referenced to keep the project timelines private + if ($in_header_lines && + ($line =~ /\s(proto\d?|evt|dvt|pvt)\s/i) { + WARN("COMMIT_LOG_PHASE_NAME", + "Commit message should generally not include phases.\n" . $herecurr); + } + # Reset possible stack dump if a blank line is found if ($in_commit_log && $commit_log_possible_stack_dump && $line =~ /^\s*$/) { -- To view, visit https://review.coreboot.org/c/coreboot/+/67347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0fe7c75cc10926a3f4713c350c39af11b62bbae Gerrit-Change-Number: 67347 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI
by Bill XIE (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Paul Menzel, Angel Pons. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67089 ) Change subject: mb/hp/z220_series: Add configs for integrated XHCI ...................................................................... Patch Set 6: (1 comment) File src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67089/comment/ff1d58e3_0ec8b779 PS6, Line 9: register "xhci_overcurrent_mapping" = "0x0000000f" > Because there is no guarantee that CMT variant has the same overcurrent mapping as SFF variant, as s […] Now I move "xhci_overcurrent_mapping" back to devicetree.cb with value "0x0000000f". -- To view, visit https://review.coreboot.org/c/coreboot/+/67089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Gerrit-Change-Number: 67089 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 16:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI
by Bill XIE (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Paul Menzel, Angel Pons. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67089 to look at the new patch set (#8). Change subject: mb/hp/z220_series: Add configs for integrated XHCI ...................................................................... mb/hp/z220_series: Add configs for integrated XHCI Without these, all SuperSpeed ports are wired to EHCI #2. "superspeed_capable_ports" and "xhci_switchable_ports" should fit both CMT and SFF variants, while "xhci_overcurrent_mapping" may be specific for a variant. With this commit, SuperSpeed devices plugged in SuperSpeed ports are wired to the XHCI on my own Z220 SFF. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc --- M src/mainboard/hp/z220_series/devicetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/67089/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Gerrit-Change-Number: 67089 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2022