coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/rex: Add memory init
by Subrata Banik (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Tarun Tuli, Tim Wawrzynczak, Kapil Porwal, Eric Lai. Subrata Banik has uploaded a new patch set (#4) to the change originally created by Eric Lai. ( https://review.coreboot.org/c/coreboot/+/64850 ) Change subject: mb/google/rex: Add memory init ...................................................................... mb/google/rex: Add memory init Add memory init with placeholder. DQ map can be auto probed by fsp. So leave it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Makefile.inc M src/mainboard/google/rex/romstage.c A src/mainboard/google/rex/spd/Makefile.inc M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc A src/mainboard/google/rex/variants/baseboard/rex/memory.c A src/mainboard/google/rex/variants/rex0/memory/Makefile.inc A src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt 10 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64850/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Gerrit-Change-Number: 64850 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/rex: Enable EC
by Subrata Banik (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Tarun Tuli, Tim Wawrzynczak, Kapil Porwal, Eric Lai. Subrata Banik has uploaded a new patch set (#10) to the change originally created by Eric Lai. ( https://review.coreboot.org/c/coreboot/+/64622 ) Change subject: mb/google/rex: Enable EC ...................................................................... mb/google/rex: Enable EC Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Makefile.inc M src/mainboard/google/rex/dsdt.asl A src/mainboard/google/rex/ec.c M src/mainboard/google/rex/mainboard.c A src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/ec.h M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h A src/mainboard/google/rex/variants/rex0/include/variant/ec.h M src/mainboard/google/rex/variants/rex0/include/variant/gpio.h 9 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/64622/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/64622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 Gerrit-Change-Number: 64622 Gerrit-PatchSet: 10 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/rex: Add flashmap descriptor
by Subrata Banik (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Eric Lai. Subrata Banik has uploaded a new patch set (#12) to the change originally created by Eric Lai. ( https://review.coreboot.org/c/coreboot/+/64590 ) Change subject: mb/google/rex: Add flashmap descriptor ...................................................................... mb/google/rex: Add flashmap descriptor Add 32MB flashmap descriptor as below: Descriptor Region -> 0 - 0x3fff (~16KB) CSE Partition -> 0x4000 - 0x8fffff (~9MB) BIOS Region -> 0x900000 - 0x1ffffff (23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7 --- A src/mainboard/google/rex/chromeos.fmd 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/64590/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/64590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7 Gerrit-Change-Number: 64590 Gerrit-PatchSet: 12 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/meteorlake: Refactor bootblock SoC programming code
by Subrata Banik (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Angel Pons, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Tim Wawrzynczak, Kapil Porwal, Angel Pons, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64793 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Refactor bootblock SoC programming code ...................................................................... soc/intel/meteorlake: Refactor bootblock SoC programming code This patch ensures the IP initialization being done as part of MTL bootblock code is able to complete the bootblock phase without any visible hang. The re-ordering in the MTL bootblock SoC programming is required to ensure the SA early initialization is taking place prior to performing any PCI Read/Write operation (like P2SB bar enabling for IOE die etc.). Additionally, Fast SPI init takes place prior to enabling ROM caching etc. BUG=b:224325352 TEST= Able to build and start booting the MTL simics. Without this change, the code execution is stuck as below: [NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz [DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG] CPU: AES supported, TXT supported, VT supported [DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG] IGD: device id ffff (rev ff) is Unknown [INFO ] PMC: Using default GPE route. [INFO ] VBNV: CMOS invalid, restoring from flash [ERROR] init_vbnv: failed to locate NVRAM [EMERG] Cannot locate primary CBFS Able to detect the Flash and reading the SPI flash layout in proper with this change as below: [NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz [DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG] CPU: AES supported, TXT supported, VT supported [DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown [INFO ] PMC: Using default GPE route. [INFO ] VBNV: CMOS invalid, restoring from flash [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000. [DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33 [DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes) [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a --- M src/soc/intel/meteorlake/bootblock/bootblock.c M src/soc/intel/meteorlake/bootblock/soc_die.c 2 files changed, 20 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/64793/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Gerrit-Change-Number: 64793 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/var/kuldax: Update overridetree
by David Wu (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64888 to look at the new patch set (#2). Change subject: mb/google/brask/var/kuldax: Update overridetree ...................................................................... mb/google/brask/var/kuldax: Update overridetree Update override devicetree based on schematics. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 --- M src/mainboard/google/brya/variants/kuldax/overridetree.cb 1 file changed, 244 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/64888/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 Gerrit-Change-Number: 64888 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/var/kuldax: update overridetree
by David Wu (Code Review) 02 Jun '22

02 Jun '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64888 ) Change subject: mb/google/brask/var/kuldax: update overridetree ...................................................................... mb/google/brask/var/kuldax: update overridetree Update override devicetree based on schematics. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 --- M src/mainboard/google/brya/variants/kuldax/overridetree.cb 1 file changed, 244 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/64888/1 diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 4f2c04a..a885d69 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -1,6 +1,248 @@ chip soc/intel/alderlake + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" - device domain 0 on - end + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "6" + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/64888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 Gerrit-Change-Number: 64888 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd/lp5: Add new LP5 part H58G56AK6BX069
by Terry Chen (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Felix Held. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64662 ) Change subject: spd/lp5: Add new LP5 part H58G56AK6BX069 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Hi Nick/Reka, Please help to review the CL. Many thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/64662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6136e17706c6248598886f8f9bd8fdd7efff4dab Gerrit-Change-Number: 64662 Gerrit-PatchSet: 8 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jun 2022 09:42:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Update gpio configuration
by Subrata Banik (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak, Zhuohao Lee. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64786 ) Change subject: mb/google/brya/var/kinox: Update gpio configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f Gerrit-Change-Number: 64786 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Jun 2022 09:23:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add support for PCI MMIO CONFIG access.
by build bot (Jenkins) (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Ravi Kumar Bokka, Shelley Chen, Furquan Shaikh, Venkat Thogaru, Sudheer Amrabadi, Arthur Heymans, Prasad Malisetty. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57615 ) Change subject: libpayload: Add support for PCI MMIO CONFIG access. ...................................................................... Patch Set 64: Verified-1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150479): https://review.coreboot.org/c/coreboot/+/57615/comment/c2719114_b01c2eac PS64, Line 6: Subject line should not end with a period. -- To view, visit https://review.coreboot.org/c/coreboot/+/57615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Gerrit-Change-Number: 57615 Gerrit-PatchSet: 64 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Jun 2022 08:46:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCI config base address and length.
by build bot (Jenkins) (Code Review) 02 Jun '22

02 Jun '22

Attention is currently required from: Ravi Kumar Bokka, Venkat Thogaru, Sudheer Amrabadi, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61773 ) Change subject: sc7280: Add PCI config base address and length. ...................................................................... Patch Set 48: Verified-1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150477): https://review.coreboot.org/c/coreboot/+/61773/comment/31f0db5c_cd3cb9b5 PS48, Line 6: Subject line should not end with a period. -- To view, visit https://review.coreboot.org/c/coreboot/+/61773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I492b2b5fb97e775e5928b1326209270f719f5651 Gerrit-Change-Number: 61773 Gerrit-PatchSet: 48 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 02 Jun 2022 08:46:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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