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Change subject: sc7280: Add PCI config base address and length.
......................................................................
Patch Set 48: Verified-1
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150477):
https://review.coreboot.org/c/coreboot/+/61773/comment/31f0db5c_cd3cb9b5
PS48, Line 6:
Subject line should not end with a period.
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 2:
(2 comments)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150473):
https://review.coreboot.org/c/coreboot/+/64884/comment/6b4cc18b_c1ab787c
PS2, Line 187: #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
please, no space before tabs
File src/soc/qualcomm/sc7280/include/soc/display/mdssreg.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150473):
https://review.coreboot.org/c/coreboot/+/64884/comment/fc3d5557_26b94e38
PS2, Line 469: SW_PIX_EXT_OVERRIDE = BIT(31),
please, no space before tabs
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Change subject: mb/google/herobrine: Add support to enable display
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150474):
https://review.coreboot.org/c/coreboot/+/64885/comment/d42b471c_ffe91af4
PS2, Line 8:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Sudheer Amrabadi has uploaded a new patch set (#99) to the change originally created by Ravi Kumar Bokka. ( https://review.coreboot.org/c/coreboot/+/53902 )
Change subject: sc7280: Add PCIe host controller driver
......................................................................
sc7280: Add PCIe host controller driver
Add support for PCIe host driver to configure
in RC (root complex) mode. Host driver will power on
the PHY, enable the PCIe link and start the bus enumeration.
BUG=b:182963902,b:216686574,b:181098581
TEST=Validated on qualcomm sc7280 development board
Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <quic_pmaliset(a)quicinc.com>
---
M src/mainboard/google/herobrine/mainboard.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
A src/soc/qualcomm/sc7280/include/soc/pcie.h
A src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h
A src/soc/qualcomm/sc7280/pcie_host.c
6 files changed, 1,590 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/53902/99
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/herobrine: Add support to enable display
......................................................................
mb/google/herobrine: Add support to enable display
This change adds support to enable edp gpios, display init for herobrine.
Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb
Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com>
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/mainboard.c
2 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/64885/2
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Hello build bot (Jenkins),
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
qualcomm/sc7280: Add support for edp and mdp driver
- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Change-Id: Iae7ede75e8e20991b7ba126059867f241e16dd4f
Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com>
---
M src/soc/qualcomm/sc7280/Kconfig
M src/soc/qualcomm/sc7280/Makefile.inc
A src/soc/qualcomm/sc7280/display/disp.c
A src/soc/qualcomm/sc7280/display/edp_aux.c
A src/soc/qualcomm/sc7280/display/edp_ctrl.c
A src/soc/qualcomm/sc7280/display/edp_phy_7nm.c
A src/soc/qualcomm/sc7280/include/soc/display/edp_aux.h
A src/soc/qualcomm/sc7280/include/soc/display/edp_ctrl.h
A src/soc/qualcomm/sc7280/include/soc/display/edp_phy.h
A src/soc/qualcomm/sc7280/include/soc/display/edp_reg.h
A src/soc/qualcomm/sc7280/include/soc/display/mdssreg.h
11 files changed, 2,965 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/64884/2
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Change subject: mb/lenovo/haswell/Kconfig: VGA_BIOS_ID depends on the installed CPU
......................................................................
Abandoned
Ok disregard. According to https://github.com/linuxhw/LsPCI all Haswells have the same 8086:0416
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
> Elyes, thank you for trying, unfortunately GCC 11.3 doesn't work too. Possible outcomes when attempting to use a coreboot+SeaBIOS on AMD Lenovo G505S built with GCC 11.3 :
>
> 1) black screen, doesn't show anything - even a SeaBIOS text interface;
> 2) shows a SeaBIOS interface which hangs on "Press ESC" (pressing ESC doesn't do anything);
> 3) shows a SeaBIOS interface which works; if I didn't choose anything, then runs a default entry (a KolibriOS ramdisk, which launched successfully the times I tried); if I chose a HDD, see "4)" and "5)"
> 4) loads GRUB from HDD - it gets a password from keyboard but hangs while decrypting a /boot;
> 5) successfully decrypts /boot and shows a GRUB menu, but later hangs on "Loading initial ramdisk" ! This booting step precedes a step of entering a key and decrypting a "/" partition of a Full Disk Encryption instal of Artix Linux (user-friendly Arch without SystemD) which I did by this manual - https://wiki.artixlinux.org/Main/InstallationWithFullDiskEncryption
>
> Meanwhile, an equal coreboot+SeaBIOS build with GCC 8.3.0 and the same contents of HDD - works perfectly all the time. I haven't yet tried a mixed build of "coreboot by new GCC, SeaBIOS by old GCC"
It looks like GCC11 aligns packed structs differently which can cause problems when writing to hardware registers. As #pragma pack is used for all the AGESA code I can see why this goes south... Maybe you can see how removing '#pragma pack(1)' from Porting.h fares?
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Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64887 )
Change subject: mb/lenovo/haswell/Kconfig: VGA_BIOS_ID depends on the installed CPU
......................................................................
mb/lenovo/haswell/Kconfig: VGA_BIOS_ID depends on the installed CPU
VGA_BIOS_ID depends on the installed CPU. It's better to remove it.
UNTESTED.
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
Change-Id: I73463e00badf520f44834e4d19919fed0646deac
---
M src/mainboard/lenovo/haswell/Kconfig
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/64887/1
diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig
index 126e92d..8d2bf99 100644
--- a/src/mainboard/lenovo/haswell/Kconfig
+++ b/src/mainboard/lenovo/haswell/Kconfig
@@ -47,10 +47,6 @@
config MAINBOARD_PART_NUMBER
default "ThinkPad T440p"
-config VGA_BIOS_ID
- string
- default "8086,0416"
-
config USBDEBUG_HCD_INDEX
int
default 2
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