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Change subject: lib/cbfs: Compare addresses instead of arrays
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> There only seems to be one occurrence in coreboot, so just let’s fix it, and keep the warning enabled.
Even with one occurrence, I think Julius's comment is still valid.
File src/lib/cbfs.c:
https://review.coreboot.org/c/coreboot/+/62827/comment/4b186758_04c08843
PS1, Line 31: _preram_cbfs_cache
> Where is this defined?
Created from linker script symbols in include/memlayout.h
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Hello build bot (Jenkins), Michał Żygowski, Martin L Roth, Matt DeVillier, Stefan Reinauer, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: payloads/tianocore: Allow custom build parameters for custom builds
......................................................................
payloads/tianocore: Allow custom build parameters for custom builds
Currently, custom TianoCore builds are allowed, but those may need
different parameters. Add a Kconfig option to specify additional
parameters to be appended to build command.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I025459ae94592103b4be0c68b422100b7c649d34
---
M payloads/external/Makefile.inc
M payloads/external/tianocore/Kconfig
M payloads/external/tianocore/Makefile
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/62497/10
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63925 )
Change subject: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS1:
> > In your case, I assume overlapping DRAM_INIT_CODE and BOOTBLOCK should be valid […]
Let's summarize what we can try:
1. Overlap DRAM_INIT_CODE and BOOTBLOCK
2. Utilize 0x00200000 (for example FMAP_CACHE and TCPA_LOG)
3. Use `OVERLAP_VERSTAGE_ROMSTAGE` instead of `OVERLAP_DECOMPRESSOR_*`
File src/soc/mediatek/mt8186/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/63924/comment/b6428203_97f0409a
PS3, Line 31: /
> should we also indicate the empty 1k-4 ?
Done
https://review.coreboot.org/c/coreboot/+/63924/comment/100efa71_e4537c2d
PS3, Line 36: /* EMPTY(0x0010f400, 3K) */
> 8195 has 12k for stack. […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.
Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none
Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8186/include/soc/memlayout.ld
1 file changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63924/4
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62494 )
Change subject: intelblocks/pep: Add display on/off notifications
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62494/comment/8c9b35f3_ea08dc1a
PS3, Line 7: intelblocks/pep: Add display on/off notifications and handle TBT displays
> Actually, it doesn't fit because this commit does too much. […]
Moved TBT related changes to CB:63980
https://review.coreboot.org/c/coreboot/+/62494/comment/af25c5f5_0df8b617
PS3, Line 8:
: Add display on and off notifications which call mainboard hooks if
: present. This allows to handle some board specific functions in user
: absence or presence (whe ndisplay goes off from inactivity or on from
: activity).
:
: Additionally notify IOM to enable or disable TBT displays on S0ix
: exit and entry respectively.
> +1
Moved TBT related changes to CB:63980
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Change subject: mb/clevo/tgl-u: Add Clevo NS50 Tiger Lake laptop support
......................................................................
mb/clevo/tgl-u: Add Clevo NS50 Tiger Lake laptop support
Change-Id: I90ad6ec1c174aa09329b4979205c41a3ec458849
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A configs/config.clevo_ns50mu
M src/mainboard/clevo/tgl-u/Kconfig
M src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/variants/ns5x/Makefile.inc
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A src/mainboard/clevo/tgl-u/variants/ns5x/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/ns5x/overridetree.cb
9 files changed, 957 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
......................................................................
mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
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---
A configs/config.clevo_nv4x
A src/mainboard/clevo/tgl-u/Kconfig
A src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/Makefile.inc
A src/mainboard/clevo/tgl-u/acpi/mainboard.asl
A src/mainboard/clevo/tgl-u/acpi/sleep.asl
A src/mainboard/clevo/tgl-u/board.fmd
A src/mainboard/clevo/tgl-u/board_info.txt
A src/mainboard/clevo/tgl-u/bootblock.c
A src/mainboard/clevo/tgl-u/cmos.default
A src/mainboard/clevo/tgl-u/cmos.layout
A src/mainboard/clevo/tgl-u/dsdt.asl
A src/mainboard/clevo/tgl-u/memory.c
A src/mainboard/clevo/tgl-u/ramstage.c
A src/mainboard/clevo/tgl-u/romstage.c
A src/mainboard/clevo/tgl-u/smihandler.c
A src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h
A src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc
A src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt
A src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt
A src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c
A src/mainboard/clevo/tgl-u/variants/nv4x/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb
A src/mainboard/clevo/tgl-u/vboot-rwa.fmd
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: payloads/tianocore: Allow custom build parameters for custom builds
......................................................................
payloads/tianocore: Allow custom build parameters for custom builds
Currently, custom TianoCore builds are allowed, but those may need
different parameters. Add a Kconfig option to specify additional
parameters to be appended to build command.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I025459ae94592103b4be0c68b422100b7c649d34
---
M payloads/external/Makefile.inc
M payloads/external/tianocore/Kconfig
M payloads/external/tianocore/Makefile
3 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/62497/9
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