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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
First try of an ACPI SSDT extension. Please have a look, at least it resolves my issue on mc_apl4.
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
On Apollo Lake the fast SPI controller is located on a multi-function
PCI device which is hidden after coreboot passes over to the payload.
This makes it impossible for the OS to probe the PCI device and
therefore the OS is not aware of the resources the SPI controller has
occupied. In some circumstances it is possible that the OS moves other
PCI resources around and therefore a conflict can be introduced where
the moved resource will shadow the fast SPI BAR. This will make the SPI
controller inaccessible from the OS.
On current master the siemens mainboard mc_apl4 is affected by this
issue and all other Apollo Lake based boards are potentially affected,
too. This patch adds a SSDT extension to the common SPI driver which for
now is only handling the fast SPI controller of Apollo Lake. It reports
the BAR0 resource of the fast SPI controller via ACPI to the OS. Since
there is no defined ACPI ID for the fast SPI controller of Apollo Lake
available now, the generic one (PNP0C02) is used.
Test: Boot mc_apl4 and make sure flashrom works again.
Change-Id: Ifa89cdf41f42d4df5b46f095e22924157d9f3c3f
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/common/block/spi/spi.c
1 file changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63982/1
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 0716e1a..07a2fe2 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -2,6 +2,8 @@
#define __SIMPLE_DEVICE__
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
@@ -106,6 +108,74 @@
return spi_soc_devfn_to_bus(dev->path.pci.devfn);
}
+#if CONFIG(HAVE_ACPI_TABLES)
+/*
+ * Generate an ACPI entry for the SPI controller. This way the allocated resources
+ * for the SPI controller can be communicated to the OS even if the device is
+ * not visible on PCI (because it is hidden) and therefore can not be probed by the OS.
+ */
+static void spi_fill_ssdt(const struct device *dev)
+{
+ const char *scope = acpi_device_scope(dev);
+ const char *hid = acpi_device_hid(dev);
+ struct resource *res;
+
+ if (!scope || !hid)
+ return;
+
+ res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res)
+ return;
+
+ /* Scope */
+ acpigen_write_scope(scope);
+
+ /* Device */
+ acpigen_write_device(acpi_device_name(dev));
+ acpigen_write_name_string("_HID", hid);
+ acpi_device_write_uid(dev);
+ acpigen_write_name_string("_DDN", "ACPI Fast SPI");
+ acpigen_write_STA(acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+
+ /* Add BAR0 resource. */
+ acpigen_write_mem32fixed(1, res->base, res->size);
+
+ acpigen_write_resourcetemplate_footer();
+
+ acpigen_pop_len(); /* Device */
+ acpigen_pop_len(); /* Scope */
+}
+
+/*
+ * For now this ACPI extension is enabled just for the fast SPI controller on Apollo Lake.
+ * as there is no official ACPI ID for this controller use the generic PNP ID for now.
+ */
+
+static const char *spi_acpi_hid(const struct device *dev)
+{
+ switch (dev->device) {
+ case PCI_DID_INTEL_APL_HWSEQ_SPI:
+ return "PNP0C02";
+ default:
+ return NULL;
+ }
+}
+
+static const char *spi_acpi_name(const struct device *dev)
+{
+ switch (dev->device) {
+ case PCI_DID_INTEL_APL_HWSEQ_SPI:
+ return "FSPI";
+ default:
+ return NULL;
+ }
+}
+#endif
+
static struct spi_bus_operations spi_bus_ops = {
.dev_to_bus = &spi_dev_to_bus,
};
@@ -117,6 +187,11 @@
.scan_bus = scan_generic_bus,
.ops_spi_bus = &spi_bus_ops,
.ops_pci = &pci_dev_ops_pci,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt = spi_fill_ssdt,
+ .acpi_hid = spi_acpi_hid,
+ .acpi_name = spi_acpi_name,
+#endif
};
static const unsigned short pci_device_ids[] = {
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Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63546/comment/30b8663f_553c5b3f
PS6, Line 11: This
> These
Done
https://review.coreboot.org/c/coreboot/+/63546/comment/addcb728_acb6faca
PS6, Line 9: There are two APL specific config switches for RAPL and min. cpu clock
: (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO).
: This switches could be used in future in other CPU platforms.
: Move them to common code instead of having them just for one SOC.
> Please do not wrap lines, just because a sentence ends.
Done
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
mb/siemens/mc_ehl: Disable RAPL
Disable RAPL for all mainboards based on mc_ehl.
Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.
Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/8
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
......................................................................
soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
Other than on previouse SOCs this needs to be done in an MCHBAR mapped
register rather than via MSR on Elkhart Lake.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/soc/intel/elkhartlake/include/soc/systemagent.h
M src/soc/intel/elkhartlake/systemagent.c
2 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63547/7
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Hello build bot (Jenkins), Werner Zeh, Andrey Petrov,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common
......................................................................
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/Kconfig
9 files changed, 26 insertions(+), 27 deletions(-)
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Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63548/comment/a65554f1_82553586
PS7, Line 9: Disable RAPL for all mainboards based on mc_ehl.
> Why?
For stable real time mode of the CPUs.
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Hello Arthur Heymans, build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, Angel Pons, Nill Ge, Marc Jones, Subrata Banik, lichenchen.carl, Tim Chu, Shelly Chang,
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Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
......................................................................
arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
1. Add Kconfig SMBIOS_TYPE17_EMPTY_SLOT that can create SMBIOS
type 17 tables for empty DIMM slots that don't have DIMM installed,
this feature is desirable for server platforms.
Mainboard can override mainboard_check_slot_exist to avoid
creating empty DIMM tables that don't exist on the board.
2. SMBIOS type 19 and 20 need to ignore meminfo->dimm_cnt array
boundary check when SMBIOS_TYPE17_EMPTY_SLOT is selected,
because meminfo->dimm would contain not only the installed DIMM.
3. Avoid creating type 20 when the DIMM size is zero.
Signed-off-by: Lichenchen Carl <lichenchen.carl(a)bytedance.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Change-Id: Ia3ff1353667f9d3bd302db42c739b7be9d3f4a32
---
M src/Kconfig
M src/arch/x86/smbios.c
M src/arch/x86/smbios_defaults.c
M src/include/memory_info.h
M src/include/smbios.h
5 files changed, 102 insertions(+), 4 deletions(-)
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Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
......................................................................
Patch Set 7:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/63882/comment/29aa8da5_111a7bc0
PS6, Line 288: return 0;
> Move the assignment to *t below the if statement?
Done
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63882 )
Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
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Patch Set 7:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/63882/comment/43041dac_8346e699
PS2, Line 814: SMBIOS_TYPE17_EMPTY_SLOT
> I'm not aware of any software that checks for empty DIMM slots.
Because for now all SOC codes hasn't implemented saving empty DIMM data into meminfo>dimm array, I think we still need to have this Kconfig and default set to n.
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