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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS5:
> Thanks Subrata. […]
Added to the relation chain (split the new names from the rest of the change)
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Change subject: soc/intel/alderlake: add missing ACPI device path names
......................................................................
soc/intel/alderlake: add missing ACPI device path names
A few ACPI device path name handlers are missing. Add handling
to ensure that these names are returned during acpi_device_path()
calls.
TEST=Built and tested on brya
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/uart/uart.c
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63984/1
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 699b39d..59f0066 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -75,6 +75,7 @@
case SA_DEVFN_TBT2: return "TRP2";
case SA_DEVFN_TBT3: return "TRP3";
case SA_DEVFN_IPU: return "IPU0";
+ case SA_DEVFN_DPTF: return "DPTF";
case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0";
@@ -111,6 +112,9 @@
case PCH_DEVFN_HDA: return "HDAS";
case PCH_DEVFN_SMBUS: return "SBUS";
case PCH_DEVFN_GBE: return "GLAN";
+ case PCH_DEVFN_SRAM: return "SRAM";
+ case PCH_DEVFN_SPI: return "FSPI";
+ case PCH_DEVFN_CSE: return "HEC1";
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
case PCH_DEVFN_EMMC: return "EMMC";
#endif
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 12f2882..3e2e697 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -308,24 +308,28 @@
static const char *uart_acpi_name(const struct device *dev)
{
switch (dev->device) {
+ case PCI_DID_INTEL_ADP_P_UART0:
case PCI_DID_INTEL_APL_UART0:
case PCI_DID_INTEL_GLK_UART0:
case PCI_DID_INTEL_SPT_UART0:
case PCI_DID_INTEL_SPT_H_UART0:
case PCI_DID_INTEL_CNP_H_UART0:
return "UAR0";
+ case PCI_DID_INTEL_ADP_P_UART1:
case PCI_DID_INTEL_APL_UART1:
case PCI_DID_INTEL_GLK_UART1:
case PCI_DID_INTEL_SPT_UART1:
case PCI_DID_INTEL_SPT_H_UART1:
case PCI_DID_INTEL_CNP_H_UART1:
return "UAR1";
+ case PCI_DID_INTEL_ADP_P_UART2:
case PCI_DID_INTEL_APL_UART2:
case PCI_DID_INTEL_GLK_UART2:
case PCI_DID_INTEL_SPT_UART2:
case PCI_DID_INTEL_SPT_H_UART2:
case PCI_DID_INTEL_CNP_H_UART2:
return "UAR2";
+ case PCI_DID_INTEL_ADP_P_UART3:
case PCI_DID_INTEL_GLK_UART3:
return "UAR3";
default:
--
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#12).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 409 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/12
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Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
......................................................................
Patch Set 5:
(3 comments)
File src/drivers/gfx/nvidia/optimus/optimus.c:
https://review.coreboot.org/c/coreboot/+/62496/comment/39ec2bb8_8922a763
PS5, Line 88: windows
Windows
https://review.coreboot.org/c/coreboot/+/62496/comment/e9f8a7ed_336add04
PS5, Line 137: if (config->reset_gpio.pin_count) {
I haven't seen the specification for this device, but shouldn't there be a delay between enabling clocks and de-asserting reset signal?
https://review.coreboot.org/c/coreboot/+/62496/comment/c1585144_4f078f4f
PS5, Line 261: const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000);
Please split this line.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 )
Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 17:
(11 comments)
File src/soc/amd/common/block/psp/psb.c:
https://review.coreboot.org/c/coreboot/+/60968/comment/ea39bfbd_e17926e1
PS17, Line 18: /* PSB Test Status and Error Codes (doc#56654) */
> As psb_test_status_to_string() is called in error scenarios so all error status codes are mentioned […]
See my comments below, PSB_TEST_STATUS_PASS can be used in the check before printing the error string.
https://review.coreboot.org/c/coreboot/+/60968/comment/1b491b37_b8e7741d
PS17, Line 30:
> As fuse_status_to_string() is called in error scenarios, so all error status codes are mentioned and […]
See my comments below, FUSE_STATUS_SUCCESS can be used in the check before printing the error string.
https://review.coreboot.org/c/coreboot/+/60968/comment/3527710d_bf808e25
PS17, Line 35: error:
Is this prefix needed? These strings are printed with BIOS_ERR log level.
https://review.coreboot.org/c/coreboot/+/60968/comment/a0fc3b8f_9e54a702
PS17, Line 35: static const char *psb_test_status_fuse_read_err = "error: Error reading fuse info";
:
: static const char *psb_test_status_bios_key_bad_usage =
: "error: OEM BIOS signing key usage flag violation";
:
: static const char *psb_test_status_bios_rtm_sig_noent =
: "error: BIOS RTM signature entry not found";
:
: static const char *psb_test_status_bios_rtm_copy_err =
: "error: BIOS copy to DRAM failed";
:
: static const char *psb_test_status_bios_rtm_bad_sig =
: "error: BIOS RTM signature verification failed";
:
: static const char *psb_test_status_bios_key_bad_sig =
: "error: OEM BIOS signing key failed signature verification";
:
: static const char *psb_test_status_platform_bad_id =
: "error: Platform vendor id and/or model id binding violation";
:
: static const char *psb_test_status_bios_copy_bit_unset =
: "error: BIOS copy bit unset for reset image";
:
: static const char *psb_test_status_bios_ca_bad_sig =
: "error: OEM BIOS signing CA key failed signature verification";
:
: static const char *psb_test_status_bios_ca_bad_usage =
: "error: OEM BIOS signing CA key usage flag violation";
:
: static const char *psb_test_status_bios_key_bad_revision =
: "error: OEM BIOS signing key revision violation";
:
: static const char *psb_test_status_unknown = "error: Unknown failure";
Why not use the string literals directly in the code?
https://review.coreboot.org/c/coreboot/+/60968/comment/2105fb49_1bb76560
PS17, Line 127: read32
You can use `read32p` and drop the cast
https://review.coreboot.org/c/coreboot/+/60968/comment/2c6bc98d_81b070df
PS17, Line 167: psb_test_status = status & PSB_TEST_STATUS_MASK;
nit: I'd make this const and declare/initialize it in one line:
const u32 psb_test_status = status & PSB_TEST_STATUS_MASK;
https://review.coreboot.org/c/coreboot/+/60968/comment/76dd6ce9_6b042def
PS17, Line 169: if (psb_test_status) {
This assumes that 0 means success. Why not make it explicit by defining `PSB_TEST_STATUS_PASS` as Felix Held suggested?
if (psb_test_status != PSB_TEST_STATUS_PASS)
https://review.coreboot.org/c/coreboot/+/60968/comment/1223879f_b7b26643
PS17, Line 181: cmd_status = send_psp_command(MBOX_BIOS_CMD_PSB_AUTO_FUSING, &buffer);
nit: I'd make this const and declare/initialize it in one line:
const int cmd_status = send_psp_command(MBOX_BIOS_CMD_PSB_AUTO_FUSING, &buffer);
https://review.coreboot.org/c/coreboot/+/60968/comment/e094ee4f_37a280b6
PS17, Line 190: fuse_status = read32(&buffer.header.status);
nit: I'd make this const and declare/initialize it in one line:
const u32 fuse_status = read32(&buffer.header.status);
https://review.coreboot.org/c/coreboot/+/60968/comment/d2de3ed8_3825e166
PS17, Line 191: if (fuse_status) {
This assumes that 0 means success. Why not make it explicit by defining `FUSE_STATUS_SUCCESS` as Felix Held suggested?
if (fuse_status != FUSE_STATUS_SUCCESS)
https://review.coreboot.org/c/coreboot/+/60968/comment/81dab1ae_291564c2
PS17, Line 206: *
nit: drop empty comment line
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Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/ec/clevo/it5570/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/62495/comment/5b629193_4f16b4df
PS5, Line 100: Method (I2ER, 1, NotSerialized)
> Since this method is a sequence of writes to the same locations, shouldn't it be serialized?
+1
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#11).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 412 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/11
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#10).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 412 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/10
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Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
......................................................................
Patch Set 5:
(2 comments)
File src/ec/clevo/it5570/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/62495/comment/d8c9e52c_b900ecd5
PS5, Line 100: Method (I2ER, 1, NotSerialized)
Since this method is a sequence of writes to the same locations, shouldn't it be serialized?
https://review.coreboot.org/c/coreboot/+/62495/comment/15dd94eb_f951b170
PS5, Line 118: Method (I2EW, 2, NotSerialized)
Ditto
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
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