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Change in coreboot[master]: arch/x86/acpi: Consolidate POST code handling
by Angel Pons (Code Review) 02 May '22

02 May '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63988 ) Change subject: arch/x86/acpi: Consolidate POST code handling ...................................................................... arch/x86/acpi: Consolidate POST code handling Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/arch/x86/acpi/post.asl M src/mainboard/asus/p2b/dsdt.asl M src/mainboard/intel/cedarisland_crb/acpi/platform.asl M src/soc/intel/common/acpi/platform.asl M src/southbridge/intel/common/acpi/platform.asl 5 files changed, 21 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63988/1 diff --git a/src/arch/x86/acpi/post.asl b/src/arch/x86/acpi/post.asl new file mode 100644 index 0000000..dbdc681 --- /dev/null +++ b/src/arch/x86/acpi/post.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(POST_IO) + +/* POST code support, typically on port 80 */ +OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +#else + +/* Dummy placeholder to avoid issues */ +Name (DBG0, 0) + +#endif diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 25515d2..5d53c1d 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,13 +22,7 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - /* Port 80 POST */ - - OperationRegion (POST, SystemIO, 0x80, 1) - Field (POST, ByteAcc, Lock, Preserve) - { - DBG0, 8 - } + #include <arch/x86/acpi/post.asl> /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl index 3bebbff..5f7ffbb 100644 --- a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> Name(\APC1, Zero) // IIO IOAPIC diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 3bb2f53..c988e0a 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -7,13 +7,7 @@ External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index ec7d680..e044f04 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -9,13 +9,7 @@ APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include <arch/x86/acpi/post.asl> #if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Gerrit-Change-Number: 63988 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff
by Angel Pons (Code Review) 02 May '22

02 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63987 ) Change subject: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff ...................................................................... mb/asus/p2b/dsdt.asl: Align POST code ASL stuff Align POST code ASL elements with existing code in newer southbridges. The main differences are that `NoLock` is changed to `Lock`, and that names have been changed. The lock type change should not be a problem because the field is only used once in the _PTS method. Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p2b/dsdt.asl 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63987/1 diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 2c88cf6..25515d2 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,10 +22,12 @@ #include <acpi/dsdt_top.asl> /* \_SB scope defining the main processor is generated in SSDT. */ - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) + /* Port 80 POST */ + + OperationRegion (POST, SystemIO, 0x80, 1) + Field (POST, ByteAcc, Lock, Preserve) { - P80, 8 + DBG0, 8 } /* @@ -77,7 +79,7 @@ /* Arms SMI for device 12 */ TO12 = 1 /* Put out a POST code */ - P80 = Arg0 | 0xF0 + DBG0 = Arg0 | 0xF0 } Method (\_WAK, 1, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/63987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b Gerrit-Change-Number: 63987 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/acpi/debug.asl: Drop POST code stuff
by Angel Pons (Code Review) 02 May '22

02 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63986 ) Change subject: arch/x86/acpi/debug.asl: Drop POST code stuff ...................................................................... arch/x86/acpi/debug.asl: Drop POST code stuff To pave the way for future refactoring commits, drop POST code elements from the debug.asl file. Only msi/ms7721 includes debug.asl and it does not use any of it anyway. Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/acpi/debug.asl 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63986/1 diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index cee85e5..fe71b3e 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* -* 0x80: POST_BASE * 0x3F8: DEBCOM_BASE -* X80: POST_REGION -* P80: PORT80 * * CREG: DEBCOM_REGION * CUAR: DEBCOM_UART @@ -17,12 +14,6 @@ * DEBUG_INIT DINI */ -OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) -{ - P80, 8 -} - OperationRegion(CREG, SystemIO, 0x3F8, 8) Field(CREG, ByteAcc, NoLock, Preserve) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3 Gerrit-Change-Number: 63986 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/amd: Simplify fx_devs usage
by Michał Kopeć (Code Review) 02 May '22

02 May '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63985 ) Change subject: northbridge/amd: Simplify fx_devs usage ...................................................................... northbridge/amd: Simplify fx_devs usage Only single-node plaforms are actually supported, so arrays of fx_devs will always contain just one element. Remove the arrays. TEST=Boot PC Engines apu1 (F14h) and apu2 (00730F01) into operating system. F15tn and F16kb remain untested. Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I7e4385835769d4d90520e3d645ba853ef0d12803 --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 4 files changed, 110 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63985/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e4cd187..f4131d8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -18,12 +18,10 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h> -#define FX_DEVS 1 - -static struct device *__f0_dev[FX_DEVS]; -static struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0; static u32 get_io_addr_index(u32 nodeid, u32 linkn) @@ -44,10 +42,10 @@ /* io range allocation */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); } static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, @@ -57,50 +55,41 @@ u32 tempreg; /* io range allocation */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg + 4, tempreg); + pci_write_config32(__f1_dev, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); } static void get_fx_devs(void) { - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i + 1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } + + fx_devs = 1; } static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); } static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } } @@ -134,7 +123,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -285,8 +274,8 @@ u64 basek, limitk; u32 hole; - if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { - hole = pci_read_config32(__f1_dev[0], 0xf0); + if (get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) { + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole @@ -444,20 +433,13 @@ limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } + unsigned int reg_link; reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { + if (__f0_dev) { /* Reserve the resource */ struct resource *res; res = - new_resource(reg_dev, + new_resource(__f0_dev, IOINDEX(0x1000 + reg, reg_link)); if (res) { @@ -524,7 +506,7 @@ idx = 0x10; u64 basek, limitk, sizek; // 4 1T - if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { + if (get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) { sizek = limitk - basek; printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2d7e93b..59e141b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -22,83 +22,65 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> -#define MAX_NODE_NUMS MAX_NODES - static unsigned int node_nums; static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0; static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); } -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); } static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + + fx_devs = 1; } static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); } static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } } @@ -135,7 +117,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -308,7 +290,7 @@ set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);// [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -564,7 +546,7 @@ nodeid = (limit & 0xf) + ((base>>4)&0x30); } reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; + reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res; @@ -595,9 +577,9 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -612,7 +594,7 @@ resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -677,7 +659,7 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index e754f99..3d7b343 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -26,79 +26,63 @@ static unsigned int node_nums; static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0; static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); } static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); } static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + + fx_devs = 1; } static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); } static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } } @@ -135,7 +119,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -582,7 +566,7 @@ nodeid = (limit & 0xf) + ((base>>4)&0x30); } reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; + reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res; @@ -613,9 +597,9 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -630,7 +614,7 @@ resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -695,7 +679,7 @@ for (i = 0; i < node_nums; i++) { resource_t basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6bc313d..f90a64e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -25,21 +25,15 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h> -#define MAX_NODE_NUMS MAX_NODES #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0; -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); -} - static struct device *get_mc_dev(void) { return pcidev_on_root(DEV_CDB, 0); @@ -59,32 +53,27 @@ static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); + + fx_devs = 1; } static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } } @@ -120,10 +109,10 @@ get_fx_devs(); /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ - if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + if (pci_read_config32(__f2_dev, 0x118) & (1 << 18)) { /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ u64 basek, limitk; - if (!get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) return; mmio_resource(dev, index++, limitk, 16*1024); } @@ -718,9 +707,9 @@ for (i = 0; i < get_node_nums(); i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -735,7 +724,7 @@ resource_t limitk_pri = 0; for (i = 0; i < get_node_nums(); i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -785,7 +774,7 @@ for (i = 0; i < get_node_nums(); i++) { u64 basek, limitk, sizek; // 4 1T - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node sizek = limitk - basek; -- To view, visit https://review.coreboot.org/c/coreboot/+/63985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e4385835769d4d90520e3d645ba853ef0d12803 Gerrit-Change-Number: 63985 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Michał Kopeć (Code Review) 02 May '22

02 May '22

Attention is currently required from: Nico Huber, Michał Żygowski, Paul Menzel, Angel Pons, Felix Held. Michał Kopeć has uploaded a new patch set (#14) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... nb/amd/agesa/family14/northbridge.c: Report missing resources Not all resources were being reported, add them: 0xa0000 - 0xbffff: legacy VGA 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) CC6 DRAM TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 50 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Use generic allocation functions for PCI domain
by Michał Kopeć (Code Review) 02 May '22

02 May '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Michał Kopeć has uploaded a new patch set (#11) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/53954 ) Change subject: nb/amd/agesa/family14: Use generic allocation functions for PCI domain ...................................................................... nb/amd/agesa/family14: Use generic allocation functions for PCI domain Move the DRAM reporting to read_resoures function before the resources are being set. Use generic PCI domain resource allocation functions to read and set domain resources. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3 --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 5 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/53954/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/53954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3 Gerrit-Change-Number: 53954 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Use generic allocation functions for northbridge
by Michał Kopeć (Code Review) 02 May '22

02 May '22

Attention is currently required from: Nico Huber, Michał Żygowski, Michał Kopeć, Piotr Król. Michał Kopeć has uploaded a new patch set (#11) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52934 ) Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge ...................................................................... nb/amd/agesa/family14: Use generic allocation functions for northbridge Remove obsolete resource assigning functions. IO and MMIO address registers are currently set by amd_initcpuio to cover whole PCI hole under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to southbridge already. Use generic PCI and resource allocation functions wherever possible to set northbridge resources. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 7 insertions(+), 243 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/52934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a Gerrit-Change-Number: 52934 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intelblocks/pep: Handle TBT displays on s0ix transition
by Angel Pons (Code Review) 02 May '22

02 May '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak, Michał Kopeć. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63980 ) Change subject: intelblocks/pep: Handle TBT displays on s0ix transition ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f49d8e30fe8e8b335128e53d71ef902328f031a Gerrit-Change-Number: 63980 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 02 May 2022 14:42:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks/pep: Add display on/off notifications
by Angel Pons (Code Review) 02 May '22

02 May '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62494 ) Change subject: intelblocks/pep: Add display on/off notifications ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62494/comment/6b1a2507_d8cdf4f4 PS3, Line 7: intelblocks/pep: Add display on/off notifications and handle TBT displays > Moved TBT related changes to CB:63980 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Gerrit-Change-Number: 62494 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 02 May 2022 14:41:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add missing ACPI device path names
by Tarun Tuli (Code Review) 02 May '22

02 May '22

Attention is currently required from: Tim Wawrzynczak. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63984 ) Change subject: soc/intel/alderlake: Add missing ACPI device path names ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63984/comment/d58cd6a5_40949c0f PS1, Line 7: a > `A` in caps Ack https://review.coreboot.org/c/coreboot/+/63984/comment/58af7523_6d9d24c3 PS1, Line 9: > remove one space Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Gerrit-Change-Number: 63984 Gerrit-PatchSet: 2 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 May 2022 14:20:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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