coreboot-gerrit May 2022

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Change in coreboot[master]: soc/intel/alderlake: Add missing ACPI device path names
by Tarun Tuli (Code Review) 02 May '22

02 May '22

Attention is currently required from: Tarun Tuli, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63984 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add missing ACPI device path names ...................................................................... soc/intel/alderlake: Add missing ACPI device path names A few ACPI device path name handlers are missing. Add handling to ensure that these names are returned during acpi_device_path() calls. TEST=Built and tested on brya Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/common/block/uart/uart.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63984/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Gerrit-Change-Number: 63984 Gerrit-PatchSet: 2 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: add missing ACPI device path names
by Subrata Banik (Code Review) 02 May '22

02 May '22

Attention is currently required from: Tarun Tuli, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63984 ) Change subject: soc/intel/alderlake: add missing ACPI device path names ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63984/comment/e2cd54ba_e4a00666 PS1, Line 7: a `A` in caps https://review.coreboot.org/c/coreboot/+/63984/comment/332199b6_2145b6eb PS1, Line 9: remove one space -- To view, visit https://review.coreboot.org/c/coreboot/+/63984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Gerrit-Change-Number: 63984 Gerrit-PatchSet: 1 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 May 2022 14:15:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76: Configure I2C HID IRQs as level triggered
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61343 ) Change subject: mb/system76: Configure I2C HID IRQs as level triggered ...................................................................... mb/system76: Configure I2C HID IRQs as level triggered Per Microsoft's spec for HID over I2C [1], interrupts must be level triggered. Switch GPIOs and the devicetree config to conform to this. Touchpad and multitouch gestures were already working, so no behavior changes are observed in normal use. [1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/system76/addw1/variants/addw1/gpio.c M src/mainboard/system76/addw1/variants/addw1/overridetree.cb M src/mainboard/system76/addw1/variants/addw2/gpio.c M src/mainboard/system76/addw1/variants/addw2/overridetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/gpio.c M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp6/variants/oryp6/gpio.c M src/mainboard/system76/whl-u/gpio.c M src/mainboard/system76/whl-u/variants/darp5/overridetree.cb 12 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/variants/addw1/gpio.c b/src/mainboard/system76/addw1/variants/addw1/gpio.c index 179e9eb..5f97d88 100644 --- a/src/mainboard/system76/addw1/variants/addw1/gpio.c +++ b/src/mainboard/system76/addw1/variants/addw1/gpio.c @@ -49,7 +49,7 @@ PAD_NC(GPP_B1, NONE), PAD_NC(GPP_B2, NONE), // PCH_GPP_B3 (touchpad interrupt) - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST), PAD_NC(GPP_B4, NONE), PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ# PAD_NC(GPP_B6, NONE), diff --git a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb index ada23b2..1a1f8b4 100644 --- a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb @@ -11,7 +11,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/addw1/variants/addw2/gpio.c b/src/mainboard/system76/addw1/variants/addw2/gpio.c index c699fd0..e635555 100644 --- a/src/mainboard/system76/addw1/variants/addw2/gpio.c +++ b/src/mainboard/system76/addw1/variants/addw2/gpio.c @@ -33,7 +33,7 @@ PAD_NC(GPP_A11, UP_20K), PAD_NC(GPP_A12, NONE), PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# - PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT# + PAD_CFG_GPI_APIC_LOW(GPP_A14, NONE, PLTRST), // TCHPD_INT# PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PW_ACK# PAD_NC(GPP_A16, DN_20K), PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET diff --git a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb index 44f945a..640f46e 100644 --- a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb @@ -12,7 +12,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A14_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 612711d..47e11d4 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -105,7 +105,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/cml-u/gpio.c b/src/mainboard/system76/cml-u/gpio.c index e3e4f54..03683ae 100644 --- a/src/mainboard/system76/cml-u/gpio.c +++ b/src/mainboard/system76/cml-u/gpio.c @@ -95,7 +95,7 @@ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD PAD_NC(GPP_C22, NONE), - PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6 + PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6 /* ------- GPIO Group D ------- */ PAD_NC(GPP_D0, NONE), diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 1723cea..ff2cdc7 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -5,7 +5,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb index e2e4d11..91127a444 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb @@ -13,7 +13,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 85b5d26..e63e136 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -101,7 +101,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/system76/oryp6/variants/oryp6/gpio.c b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c index efdb79f..e90ea87 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/gpio.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c @@ -133,7 +133,7 @@ PAD_NC(GPP_E4, NONE), PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // M2_P1_SATA_DEVSLP _PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000), // SMI# - PAD_CFG_GPI_APIC_EDGE_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# + PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# PAD_NC(GPP_E9, NONE), // USB_OC0# (test point) PAD_NC(GPP_E10, NONE), // USB_OC1# (test point) diff --git a/src/mainboard/system76/whl-u/gpio.c b/src/mainboard/system76/whl-u/gpio.c index b23d039..ca54637 100644 --- a/src/mainboard/system76/whl-u/gpio.c +++ b/src/mainboard/system76/whl-u/gpio.c @@ -95,7 +95,7 @@ //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD PAD_NC(GPP_C22, NONE), - PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C23, NONE, PLTRST), // NC on galp3-c, TP_ATTN# on darp5 + PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp3-c, TP_ATTN# on darp5 /* ------- GPIO Group GPP_D ------- */ PAD_NC(GPP_D0, NONE), diff --git a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb index 4ae96ff..0086905 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb @@ -5,7 +5,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end -- To view, visit https://review.coreboot.org/c/coreboot/+/61343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc Gerrit-Change-Number: 61343 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: Update power control settings for 15W SOC
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63899 ) Change subject: mb/google/brya/var/kinox: Update power control settings for 15W SOC ...................................................................... mb/google/brya/var/kinox: Update power control settings for 15W SOC Kinox keeps 65W barrel jack for Intel Pentium/Celeron SOC. Considering the dynamic loading of 65W adapter, it can up to 130% with 20ms. Update power settings to below for preventing blowing out the adapter. - Psys_Pmax 135W - PL2 39W - PL4 72.5W - Psys_PL2 65W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv For Intel Core processor, Kinox will use 90W barrel jack. Modify default power settings as below. - Psys_Pmax 135W - PL2 55W - PL4 123W - Psys_PL2 90W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kinox/ramstage.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Hou-hsun Lee: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/kinox/ramstage.c b/src/mainboard/google/brya/variants/kinox/ramstage.c index aa805ce..fc61e41 100644 --- a/src/mainboard/google/brya/variants/kinox/ramstage.c +++ b/src/mainboard/google/brya/variants/kinox/ramstage.c @@ -10,9 +10,9 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ - { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 39000, 39000, 72500 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, @@ -24,8 +24,8 @@ const struct system_power_limits sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ { PCI_DID_INTEL_ADL_P_ID_10, 15, 65 }, - { PCI_DID_INTEL_ADL_P_ID_7, 15, 65 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 65 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 90 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 230 }, { PCI_DID_INTEL_ADL_P_ID_5, 45, 230 }, @@ -40,23 +40,23 @@ * Given the hardware design in kinox, the serial shunt resistor is 0.01ohm. * The full scale of hardware PSYS signal 1.6v maps to system current 5A * instead of real system power. The equation is shown below: - * PSYS = 1.6v ~= (0.01ohm x 5A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) - * R501/(R501 + R510) = 0.63 = 300K / (300K + 169K) + * PSYS = 1.6v ~= (0.01ohm x 6.75A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.475 = 200K / (200K + 221K) * * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input * current and the actual system power. Since there is no voltage information * from PSYS, different voltage input would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax should be 15v x 5A = 75W - * For Type-C 20V, the Psys_pmax should be 20v x 5A = 100W - * For a barrel jack, the Psys_pmax should be 20v x 5A = 100W + * For Type-C 15V, the Psys_pmax should be 15v x 6.75A = 101.25W + * For Type-C 20V, the Psys_pmax should be 20v x 6.75A = 135W + * For a barrel jack, the Psys_pmax should be 20v x 6.75A = 135W * * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, - * and the Psys_pmax setting is 100W. Then IMVP9.1 can calculate the current system - * power = 100W * 5A / 5A = 100W, which is the actual system power. + * and the Psys_pmax setting is 135W. Then IMVP9.1 can calculate the current system + * power = 135W * 5A / 6.75A = 100W, which is the actual system power. */ const struct psys_config psys_config = { .efficiency = 97, - .psys_imax_ma = 5000, + .psys_imax_ma = 6750, .bj_volts_mv = 20000 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5 Gerrit-Change-Number: 63899 Gerrit-PatchSet: 8 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/spi: Add better error reporting to spi_flash_cmd_poll_bit
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63959 ) Change subject: drivers/spi: Add better error reporting to spi_flash_cmd_poll_bit ...................................................................... drivers/spi: Add better error reporting to spi_flash_cmd_poll_bit It's useful to know how many attempts were made at polling the status bit. BUG=b:228289365 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcc79a339707fbaab33e128807d4c0b26aa90108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63959 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/drivers/spi/spi_flash.c 1 file changed, 11 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 0142fad..9934f55 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -192,19 +192,28 @@ { const struct spi_slave *spi = &flash->spi; int ret; + int attempt = 0; u8 status; struct stopwatch sw; stopwatch_init_msecs_expire(&sw, timeout); do { + attempt++; + ret = do_spi_flash_cmd(spi, &cmd, 1, &status, 1); - if (ret) + if (ret) { + printk(BIOS_WARNING, + "SF: SPI command failed on attempt %d with rc %d\n", attempt, + ret); return -1; + } + if ((status & poll_bit) == 0) return 0; } while (!stopwatch_expired(&sw)); - printk(BIOS_WARNING, "SF: timeout at %ld msec\n", stopwatch_duration_msecs(&sw)); + printk(BIOS_WARNING, "SF: timeout at %ld msec after %d attempts\n", + stopwatch_duration_msecs(&sw), attempt); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc79a339707fbaab33e128807d4c0b26aa90108 Gerrit-Change-Number: 63959 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/spi: Convert spi_flash_cmd_poll_bit to use stopwatch API
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63939 ) Change subject: drivers/spi: Convert spi_flash_cmd_poll_bit to use stopwatch API ...................................................................... drivers/spi: Convert spi_flash_cmd_poll_bit to use stopwatch API The previous code required a bit too much effort to read. It also didn't print out the actual duration. BUG=b:228289365 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia620e789c5186f2e1d3cf3c548bda00a294d23bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/spi/spi_flash.c 1 file changed, 5 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ded88ed..0142fad 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -193,22 +193,19 @@ const struct spi_slave *spi = &flash->spi; int ret; u8 status; - struct mono_time current, end; + struct stopwatch sw; - timer_monotonic_get(&current); - end = current; - mono_time_add_msecs(&end, timeout); - + stopwatch_init_msecs_expire(&sw, timeout); do { ret = do_spi_flash_cmd(spi, &cmd, 1, &status, 1); if (ret) return -1; if ((status & poll_bit) == 0) return 0; - timer_monotonic_get(&current); - } while (!mono_time_after(&current, &end)); + } while (!stopwatch_expired(&sw)); - printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout); + printk(BIOS_WARNING, "SF: timeout at %ld msec\n", stopwatch_duration_msecs(&sw)); + return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia620e789c5186f2e1d3cf3c548bda00a294d23bf Gerrit-Change-Number: 63939 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/spi: Pretty print SPI status
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63938 ) Change subject: soc/amd/common/block/spi: Pretty print SPI status ...................................................................... soc/amd/common/block/spi: Pretty print SPI status I find it difficult to constantly decode the registers when reading them. Let's print out something that's easier to parse. BUG=b:228289365 TEST=boot guybrush and see status codes printed Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 12 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Rob Barnes: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index e8f20f3..519503d 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -39,6 +39,7 @@ { u8 dump_size; uintptr_t addr; + u32 status; if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; @@ -55,7 +56,17 @@ } printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); + + status = spi_read32(SPI_STATUS); + printk(BIOS_DEBUG, "Status: %x\n", status); + printk(BIOS_DEBUG, + " Busy: %u, FIFO Read Pointer: %u, FIFO Write Pointer: %u, Done Bytes: %u\n", + !!(status & SPI_BUSY), + (status >> SPI_FIFO_RD_PTR_SHIFT) & SPI_FIFO_RD_PTR_MASK, + (status >> SPI_FIFO_WR_PTR_SHIFT) & SPI_FIFO_WR_PTR_MASK, + (status >> SPI_DONE_BYTE_COUNT_SHIFT) & SPI_DONE_BYTE_COUNT_MASK); + + printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); addr = spi_get_bar() + SPI_FIFO; @@ -63,7 +74,6 @@ case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); break; case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); -- To view, visit https://review.coreboot.org/c/coreboot/+/63938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750 Gerrit-Change-Number: 63938 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/spi: Print error when SPI bus can't be acquired
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63937 ) Change subject: soc/amd/common/block/spi: Print error when SPI bus can't be acquired ...................................................................... soc/amd/common/block/spi: Print error when SPI bus can't be acquired Silently failing makes it hard to debug when something goes wrong. BUG=b:228289365 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b2fe13d..e8f20f3 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -139,8 +139,10 @@ return -1; } - if (wait_for_ready()) + if (wait_for_ready()) { + printk(BIOS_ERR, "FCH SPI: Failed to acquire the SPI bus\n"); return -1; + } spi_write8(SPI_CMD_CODE, cmd); spi_write8(SPI_TX_BYTE_COUNT, bytesout); -- To view, visit https://review.coreboot.org/c/coreboot/+/63937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf Gerrit-Change-Number: 63937 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/osiris: Enable EC keyboard backlight
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63952 ) Change subject: mb/google/brya/var/osiris: Enable EC keyboard backlight ...................................................................... mb/google/brya/var/osiris: Enable EC keyboard backlight Enable EC keyboard backlight for osiris. BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I501155531bff8c59641e88ea61aab623cb9a1868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63952 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/osiris/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/osiris/include/variant/ec.h b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h index 7a2a6ff..6f104d5 100644 --- a/src/mainboard/google/brya/variants/osiris/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h @@ -5,4 +5,7 @@ #include <baseboard/ec.h> +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I501155531bff8c59641e88ea61aab623cb9a1868 Gerrit-Change-Number: 63952 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Increase SPI frequency to 50 MHz
by Felix Held (Code Review) 02 May '22

02 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63948 ) Change subject: sc7280: Increase SPI frequency to 50 MHz ...................................................................... sc7280: Increase SPI frequency to 50 MHz Based on the datasheet, we can safely increase the SPI frequency of sc7280 to 50 MHz. BUG=b:190231148 BRANCH=None TEST=build and boot BIOS with this config on herobrine boards Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63948 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/qualcomm/sc7280/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 365b7d4..bdabea1 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -8,6 +8,6 @@ void bootblock_soc_init(void) { clock_init(); - quadspi_init(37500 * KHz); + quadspi_init(50000 * KHz); qupv3_fw_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35 Gerrit-Change-Number: 63948 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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