coreboot-gerrit May 2022

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Change in coreboot[master]: mb/lenovo/w541/hda_verb: Whitespace
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Attention is currently required from: Alexander Couzens. Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63994 ) Change subject: mb/lenovo/w541/hda_verb: Whitespace ...................................................................... mb/lenovo/w541/hda_verb: Whitespace Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 --- M src/mainboard/lenovo/w541/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63994/1 diff --git a/src/mainboard/lenovo/w541/hda_verb.c b/src/mainboard/lenovo/w541/hda_verb.c index a39510d..f99c393 100644 --- a/src/mainboard/lenovo/w541/hda_verb.c +++ b/src/mainboard/lenovo/w541/hda_verb.c @@ -3,7 +3,7 @@ #include <device/azalia_device.h> const u32 cim_verb_data[] = { - 0x10ec0292, /* Codec Vendor / Device ID: Realtek ALC292*/ + 0x10ec0292, /* Codec Vendor / Device ID: Realtek ALC292 */ 0x17aa2211, /* Subsystem ID */ 32, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x17aa2211), -- To view, visit https://review.coreboot.org/c/coreboot/+/63994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Gerrit-Change-Number: 63994 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/w541/dsdt.asl: Remove redundant comment
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Attention is currently required from: Felix Singer, Alexander Couzens. Hello Felix Singer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63993 to review the following change. Change subject: mb/lenovo/w541/dsdt.asl: Remove redundant comment ...................................................................... mb/lenovo/w541/dsdt.asl: Remove redundant comment Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 --- M src/mainboard/lenovo/w541/dsdt.asl 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63993/1 diff --git a/src/mainboard/lenovo/w541/dsdt.asl b/src/mainboard/lenovo/w541/dsdt.asl index e3b5070..a7afeee 100644 --- a/src/mainboard/lenovo/w541/dsdt.asl +++ b/src/mainboard/lenovo/w541/dsdt.asl @@ -19,7 +19,6 @@ #include "acpi/platform.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> - /* global NVS and variables. */ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/63993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Gerrit-Change-Number: 63993 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t440p/cmos: Remove unused options
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63992 ) Change subject: mb/lenovo/t440p/cmos: Remove unused options ...................................................................... mb/lenovo/t440p/cmos: Remove unused options Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a --- M src/mainboard/lenovo/t440p/cmos.layout 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63992/1 diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 464d242..27915d3 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -48,8 +48,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency @@ -66,8 +64,6 @@ 7 2 Keep 8 0 Secondary 8 1 Primary -9 0 AHCI -9 1 Compatible # Haswell ThinkPads have no Thinklight #10 0 Both 10 1 Keyboard -- To view, visit https://review.coreboot.org/c/coreboot/+/63992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Gerrit-Change-Number: 63992 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo: correct typo in macros
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63991 ) Change subject: lenovo: correct typo in macros ...................................................................... lenovo: correct typo in macros Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: Ia0550a115d75183cd72e478ae739731001febe22 --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/acpi/thinkpad.asl M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/w541/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig 17 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63991/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 2ea4faa9..698816f 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -28,7 +28,7 @@ Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot. -config H8_HAS_BAT_TRESHOLDS_IMPL +config H8_HAS_BAT_THRESHOLDS_IMPL bool default n diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 48e76dc..23c1e02 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -304,7 +304,7 @@ } } - #if CONFIG(H8_HAS_BAT_TRESHOLDS_IMPL) + #if CONFIG(H8_HAS_BAT_THRESHOLDS_IMPL) #include "thinkpad_bat_thresholds.asl" #endif } diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 8c53a68..f90ed53 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -9,7 +9,7 @@ select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index cff8769..3495d66 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -20,7 +20,7 @@ select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_RICOH_RCE822 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 553438f..b82f45a 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 1f715fd..2732d86 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 64a73f3..449f5c1 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select DRIVERS_RICOH_RCE822 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select EC_LENOVO_PMH7 select NO_UART_ON_SUPERIO select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index fe5b895..373d08f 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 6c4f7b0..4e14907 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select EC_LENOVO_H8 select EC_LENOVO_PMH7 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index ecd9aa9..81a1e30d 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -6,7 +6,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b3b0989..7420617 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -6,7 +6,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig index 81a3b85..507de1a 100644 --- a/src/mainboard/lenovo/w541/Kconfig +++ b/src/mainboard/lenovo/w541/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select EC_LENOVO_H8 select EC_LENOVO_PMH7 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index f514e7c..281f6b0b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index b4d677a..812ceee 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 6c174c5..abc2352 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -21,7 +21,7 @@ select MAINBOARD_HAS_TPM1 select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index d4b5bca..97ad1ac 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -7,7 +7,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index a6fd796..f966726 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T -- To view, visit https://review.coreboot.org/c/coreboot/+/63991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0550a115d75183cd72e478ae739731001febe22 Gerrit-Change-Number: 63991 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Update names and definitions for LPDDR5
by Jeremy Compostella (Code Review) 02 May '22

02 May '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Jérémy Compostella, Selma Bensaid, Paul Menzel, Angel Pons, Bernardo Perez Priego. Jeremy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Update names and definitions for LPDDR5 ...................................................................... Patch Set 11: (3 comments) File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/58101/comment/d1779e38_3c44ef30 PS11, Line 119: : DDR3_ORGANIZATION; indentation. https://review.coreboot.org/c/coreboot/+/58101/comment/ce0ef0b9_8dedec05 PS11, Line 130: : DDR3_ORGANIZATION; indentation. https://review.coreboot.org/c/coreboot/+/58101/comment/b74dfd00_6eac3b55 PS11, Line 141: : DDR3_BUS_DEV_WIDTH; indentation. -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Mon, 02 May 2022 17:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add support for catching null dereferences through debug regs
by Angel Pons (Code Review) 02 May '22

02 May '22

Attention is currently required from: Robert Zieba, Raul Rangel, Nico Huber, Tim Wawrzynczak, Paul Menzel, Arthur Heymans, Kyösti Mälkki, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63657 ) Change subject: arch/x86: Add support for catching null dereferences through debug regs ...................................................................... Patch Set 7: (1 comment) File src/arch/x86/breakpoint.c: https://review.coreboot.org/c/coreboot/+/63657/comment/c6795a2c_db72055c PS7, Line 41: = {0, 0, 0, 0} > No need, this happens automatically. If you still want to keep the initializer, you can simply use `{ 0 }` regardless of how many elements the array has. -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 May 2022 17:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [DO NOT SUBMIT] soc/intel/alderlake: Enable MCHBAR in bootblock
by Angel Pons (Code Review) 02 May '22

02 May '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63890 ) Change subject: [DO NOT SUBMIT] soc/intel/alderlake: Enable MCHBAR in bootblock ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/63890/comment/da9f323f_5de6caca PS1, Line 23: sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); > I also tried this, it's working after bootblock_systemagent_early_init function. Ah, good catch, thanks. `bootblock_systemagent_early_init()` enables PCIEXBAR, which is needed to enable MCHBAR using `sa_set_pci_bar()`. -- To view, visit https://review.coreboot.org/c/coreboot/+/63890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a9df141d475d122b22149ab18a1ae7cb068258 Gerrit-Change-Number: 63890 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 May 2022 17:02:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: Update names and definitions for LPDDR5
by Bora Guvendik (Code Review) 02 May '22

02 May '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Jérémy Compostella, Selma Bensaid, Paul Menzel, Angel Pons, Bernardo Perez Priego. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Update names and definitions for LPDDR5 ...................................................................... Patch Set 11: (1 comment) File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/58101/comment/4d3fb12c_5d034de7 PS11, Line 38: case SPD_DRAM_DDR5: > Done Can you please move these back to lines 36, 37? -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Mon, 02 May 2022 17:01:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add Raptor Lake device IDs
by Bora Guvendik (Code Review) 02 May '22

02 May '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel: Add Raptor Lake device IDs ...................................................................... Patch Set 7: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/aa9e6bda_2d0039c4 PS7, Line 3011: #define PCI_DID_INTEL_ADP_P_ESPI_32 0x5181 : #define PCI_DID_INTEL_ADP_P_ESPI_33 0x5182 : #define PCI_DID_INTEL_ADP_S_ESPI_0 0x7a80 : #define PCI_DID_INTEL_ADP_S_ESPI_1 0x7a81 : #define PCI_DID_INTEL_ADP_S_ESPI_2 0x7a82 : #define PCI_DID_INTEL_ADP_S_ESPI_3 0x7a83 : #define PCI_DID_INTEL_ADP_S_ESPI_4 0x7a84 : #define PCI_DID_INTEL_ADP_S_ESPI_5 0x7a85 : #define PCI_DID_INTEL_ADP_S_ESPI_6 0x7a86 : #define PCI_DID_INTEL_ADP_S_ESPI_7 0x7a87 : #define PCI_DID_INTEL_ADP_S_ESPI_8 0x7a88 : #define PCI_DID_INTEL_ADP_S_ESPI_9 0x7a89 : #define PCI_DID_INTEL_ADP_S_ESPI_10 0x7a8a : #define PCI_DID_INTEL_ADP_S_ESPI_11 0x7a8b : #define PCI_DID_INTEL_ADP_S_ESPI_12 0x7a8c : #define PCI_DID_INTEL_ADP_S_ESPI_13 0x7a8d : #define PCI_DID_INTEL_ADP_S_ESPI_14 0x7a8e : #define PCI_DID_INTEL_ADP_S_ESPI_15 0x7a8f : #define PCI_DID_INTEL_ADP_S_ESPI_16 0x7a90 : #define PCI_DID_INTEL_ADP_S_ESPI_17 0x7a91 : #define PCI_DID_INTEL_ADP_S_ESPI_18 0x7a92 : #define PCI_DID_INTEL_ADP_S_ESPI_19 0x7a93 : #define PCI_DID_INTEL_ADP_S_ESPI_20 0x7a94 : #define PCI_DID_INTEL_ADP_S_ESPI_21 0x7a95 : #define PCI_DID_INTEL_ADP_S_ESPI_22 0x7a96 : #define PCI_DID_INTEL_ADP_S_ESPI_23 0x7a97 : #define PCI_DID_INTEL_ADP_S_ESPI_24 0x7a98 : #define PCI_DID_INTEL_ADP_S_ESPI_25 0x7a99 : #define PCI_DID_INTEL_ADP_S_ESPI_26 0x7a9a : #define PCI_DID_INTEL_ADP_S_ESPI_27 0x7a9b : #define PCI_DID_INTEL_ADP_S_ESPI_28 0x7a9c : #define PCI_DID_INTEL_ADP_S_ESPI_29 0x7a9d : #define PCI_DID_INTEL_ADP_S_ESPI_30 0x7a9e : #define PCI_DID_INTEL_ADP_S_ESPI_31 0x7a9f : #define PCI_DID_INTEL_ADP_M_N_ESPI_0 0x5480 : #define PCI_DID_INTEL_ADP_M_N_ESPI_1 0x5481 : #define PCI_DID_INTEL_ADP_M_N_ESPI_2 0x5482 : #define PCI_DID_INTEL_ADP_M_N_ESPI_3 0x5483 : #define PCI_DID_INTEL_ADP_M_N_ESPI_4 0x5484 : #define PCI_DID_INTEL_ADP_M_N_ESPI_5 0x5485 : #define PCI_DID_INTEL_ADP_M_N_ESPI_6 0x5486 : #define PCI_DID_INTEL_ADP_M_N_ESPI_7 0x5487 : #define PCI_DID_INTEL_ADP_M_N_ESPI_8 0x5488 : #define PCI_DID_INTEL_ADP_M_N_ESPI_9 0x5489 : #define PCI_DID_INTEL_ADP_M_N_ESPI_10 0x548a : #define PCI_DID_INTEL_ADP_M_N_ESPI_11 0x548b : #define PCI_DID_INTEL_ADP_M_N_ESPI_12 0x548c : #define PCI_DID_INTEL_ADP_M_N_ESPI_13 0x548d : #define PCI_DID_INTEL_ADP_M_N_ESPI_14 0x548e : #define PCI_DID_INTEL_ADP_M_N_ESPI_15 0x548f : #define PCI_DID_INTEL_ADP_M_N_ESPI_16 0x5490 : #define PCI_DID_INTEL_ADP_M_N_ESPI_17 0x5491 : #define PCI_DID_INTEL_ADP_M_N_ESPI_18 0x5492 : #define PCI_DID_INTEL_ADP_M_N_ESPI_19 0x5493 : #define PCI_DID_INTEL_ADP_M_N_ESPI_20 0x5494 : #define PCI_DID_INTEL_ADP_M_N_ESPI_21 0x5495 : #define PCI_DID_INTEL_ADP_M_N_ESPI_22 0x5496 : #define PCI_DID_INTEL_ADP_M_N_ESPI_23 0x5497 : #define PCI_DID_INTEL_ADP_M_N_ESPI_24 0x5498 : #define PCI_DID_INTEL_ADP_M_N_ESPI_25 0x5499 : #define PCI_DID_INTEL_ADP_M_N_ESPI_26 0x549a : #define PCI_DID_INTEL_ADP_M_N_ESPI_27 0x549b : #define PCI_DID_INTEL_ADP_M_N_ESPI_28 0x548c : #define PCI_DID_INTEL_ADP_M_N_ESPI_29 0x549d : #define PCI_DID_INTEL_ADP_M_N_ESPI_30 0x549e : #define PCI_DID_INTEL_ADP_M_N_ESPI_31 0x549f : > Why are these being removed? I renamed 3 of them since they were overlapping with ADL-P / M instead added #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182 #define PCI_DID_INTEL_RPP_P_ADP_M_ESPI_6 0x5186 -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 02 May 2022 16:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: Update names and definitions for LPDDR5
by Cliff Huang (Code Review) 02 May '22

02 May '22

Attention is currently required from: Anil Kumar K, Subrata Banik, Jérémy Compostella, Selma Bensaid, Paul Menzel, Angel Pons, Bernardo Perez Priego. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Update names and definitions for LPDDR5 ...................................................................... Patch Set 11: (1 comment) File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/58101/comment/7becf930_5c985620 PS11, Line 38: case SPD_DRAM_DDR5: > this is result of merging with the CL that Anil mentioned. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Mon, 02 May 2022 16:54:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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