coreboot-gerrit May 2022

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Change in coreboot[master]: intelblocks/pep: Add display on/off notifications
by Michał Kopeć (Code Review) 02 May '22

02 May '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Patrick Rudolph. Hello build bot (Jenkins), Michał Żygowski, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62494 to look at the new patch set (#5). Change subject: intelblocks/pep: Add display on/off notifications ...................................................................... intelblocks/pep: Add display on/off notifications Add display on and off notifications which call mainboard hooks if present. This allows to handle some board specific functions in user absence or presence (when display goes off from inactivity or on from activity). TEST=Use Display on/off notification on Clevo NV41 to tell EC about laptop inactivity. It is necessary to properly handle S0ix entry (stop the fans and start blinking the power led). Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62494/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Gerrit-Change-Number: 62494 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 02 May '22

02 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 17: (1 comment) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/7edab526_b34c0c35 PS14, Line 12: #define PSB_HSTI_STATUS_OFFSET 0x10998 > Would it make sense to rename those elements (in a separate commit) to have a more descriptive name? […] description of CORE_2_PSP_MSG_38 is provided in doc#56654 under Table 1. PSB Test and HSTI State Register Bit Fields -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 17 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 May 2022 08:19:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 02 May '22

02 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Aamir Bohra, Fred Reitberger, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 17: (2 comments) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/db4b27e2_32c9c974 PS17, Line 18: /* PSB Test Status and Error Codes (doc#56654) */ > PSB_TEST_STATUS_PASS is missing As psb_test_status_to_string() is called in error scenarios so all error status codes are mentioned not the success one. Though PASS status can also be added (with PSB_TEST_STATUS_PASS is unused) for completeness, possibly for scenario where psb_test_status_to_string() is called without non-zero status check. https://review.coreboot.org/c/coreboot/+/60968/comment/4b3e40de_cfc2b0f5 PS17, Line 30: > FUSE_STATUS_SUCCESS is missing As fuse_status_to_string() is called in error scenarios, so all error status codes are mentioned and not the success one. Though SUCCESS status can also be added (with FUSE_STATUS_PASS unused) for completeness, possibly for scenario where fuse_status_to_string() is called without non-zero status check. -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 17 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 May 2022 08:16:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: xcompile: Hard-code gcc-12
by Paul Menzel (Code Review) 02 May '22

02 May '22

Attention is currently required from: Martin L Roth, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62831 ) Change subject: xcompile: Hard-code gcc-12 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62831/comment/8e0ab73f_fd75872a PS1, Line 7: xcompile: Hard-code gcc-12 > Why? It’s for testing, and not for submitting. -- To view, visit https://review.coreboot.org/c/coreboot/+/62831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8c38cbe2f76350eda7f36861523a5012a13fc0b Gerrit-Change-Number: 62831 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 02 May 2022 07:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib: endian: Qualify variable as volatile
by Paul Menzel (Code Review) 02 May '22

02 May '22

Attention is currently required from: Nico Huber, Angel Pons, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 ) Change subject: commonlib: endian: Qualify variable as volatile ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62830/comment/5d44d2d8_5ec48980 PS1, Line 9: ``` : $ make V=1 # emulation/qemu-i440fx : […] : CC ramstage/arch/x86/ebda.o : x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c : In file included from src/arch/x86/ebda.c:6: : In function 'write_ble8', : inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : In function 'write_ble8', : inlined from 'write_at_ble8' at src/commonlib/include/commonlib/endian.h:34:2, : inlined from 'write_at_le8' at src/commonlib/include/commonlib/endian.h:160:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:179:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : In function 'write_ble8', : inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:36:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : In function 'write_ble8', : inlined from 'write_at_ble8' at src/commonlib/include/commonlib/endian.h:34:2, : inlined from 'write_at_le8' at src/commonlib/include/commonlib/endian.h:160:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:179:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:36:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : In function 'write_ble8', : inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:40:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : In function 'write_ble8', : inlined from 'write_at_ble8' at src/commonlib/include/commonlib/endian.h:34:2, : inlined from 'write_at_le8' at src/commonlib/include/commonlib/endian.h:160:2, : inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:179:2, : inlined from 'setup_ebda' at src/arch/x86/ebda.c:40:2, : inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: : src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds] : 27 | *(uint8_t *)dest = val; : | ~~~~~~~~~~~~~~~~~^~~~~ : cc1: all warnings being treated as errors : ``` > Could you please replace the compiler spam with a more understandable commit message? […] See my request for help. Patchset: PS1: > I'd just abandon the change: https://gcc.gnu.org/bugzilla/show_bug. […] Yes, I am subscribed to the bug report. Despite the commit the issue at hand is still present with gcc-12 (Debian 12-20220428-1) 12.0.1 20220428 (prerelease) [gcc-12 r12-8315-g86795450041]. So, I guess it’s a valid warning. -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 02 May 2022 07:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update to GCC 11.3
by Paul Menzel (Code Review) 02 May '22

02 May '22

Attention is currently required from: Felix Singer, Martin L Roth, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63807 ) Change subject: util/crossgcc: Update to GCC 11.3 ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63807/comment/1c1b1809_10a14e3b PS1, Line 11: important > Fix line length (It was changed from 75 to 72 a while back.) https://review.coreboot.org/c/coreboot/+/63807/comment/543df2db_54108fb8 PS1, Line 17: Did you test it with one boards (QEMU for example)? Off-topic: Some scripts to compare sizes and assembler/binary changes with a compiler update would be nice. Maybe some GSOC project? -- To view, visit https://review.coreboot.org/c/coreboot/+/63807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c0aa0952f85afee59a955593c63fcfac756cc60 Gerrit-Change-Number: 63807 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 May 2022 07:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update to GCC 11.3
by Arthur Heymans (Code Review) 02 May '22

02 May '22

Attention is currently required from: Martin L Roth, Elyes Haouas. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63807 ) Change subject: util/crossgcc: Update to GCC 11.3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c0aa0952f85afee59a955593c63fcfac756cc60 Gerrit-Change-Number: 63807 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 May 2022 07:49:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: Provide RAPL and min clock ratio switches in common
by Paul Menzel (Code Review) 02 May '22

02 May '22

Attention is currently required from: Uwe Poeche, Werner Zeh, Andrey Petrov. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63546 ) Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63546/comment/c087f28f_5a8cbb3c PS6, Line 11: This These https://review.coreboot.org/c/coreboot/+/63546/comment/c37708df_d2e0e75b PS6, Line 9: There are two APL specific config switches for RAPL and min. cpu clock : (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). : This switches could be used in future in other CPU platforms. : Move them to common code instead of having them just for one SOC. Please do not wrap lines, just because a sentence ends. -- To view, visit https://review.coreboot.org/c/coreboot/+/63546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Gerrit-Change-Number: 63546 Gerrit-PatchSet: 6 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 02 May 2022 07:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Disable RAPL
by Paul Menzel (Code Review) 02 May '22

02 May '22

Attention is currently required from: Uwe Poeche, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63548 ) Change subject: mb/siemens/mc_ehl: Disable RAPL ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63548/comment/dcffc593_ce9aada9 PS7, Line 9: Disable RAPL for all mainboards based on mc_ehl. Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/63548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Gerrit-Change-Number: 63548 Gerrit-PatchSet: 7 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 02 May 2022 07:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Disable RAPL
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Attention is currently required from: Werner Zeh. Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63548 ) Change subject: mb/siemens/mc_ehl: Disable RAPL ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63548/comment/f725ce5c_c8440cca PS2, Line 9: With that patch RAPL for the mentioned mainboards is deactivated. > Maybe better: […] Done https://review.coreboot.org/c/coreboot/+/63548/comment/965c46c3_4783b216 PS2, Line 11: mc_ehl1 with and without this patch and check the mchbar : register. > Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Done Commit Message: https://review.coreboot.org/c/coreboot/+/63548/comment/7d1e636f_25ef304b PS6, Line 11: > One extra space. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Gerrit-Change-Number: 63548 Gerrit-PatchSet: 7 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 02 May 2022 07:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2022