Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63548
to look at the new patch set (#5).
Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
mb/siemens/mc_ehl: Disable RAPL
Disable RAPL for all mainboards based on mc_ehl.
Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.
Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Gerrit-Change-Number: 63548
Gerrit-PatchSet: 5
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Uwe Poeche.
Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63547
to look at the new patch set (#5).
Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
......................................................................
soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
Other than on previouse SOCs this needs to be done in an MCHBAR mapped
register rather than via MSR on Elkhart Lake.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/soc/intel/elkhartlake/include/soc/systemagent.h
M src/soc/intel/elkhartlake/systemagent.c
2 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63547/5
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Gerrit-Change-Number: 63547
Gerrit-PatchSet: 5
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
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Hello build bot (Jenkins), Werner Zeh, Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63546
to look at the new patch set (#5).
Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common
......................................................................
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO).
This switches could be used in future in other CPU platforms.
Move them to common code instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610)
do not change with this patch applied on mc_apl{1,4,5} mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/Kconfig
9 files changed, 26 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/5
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Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Gerrit-Change-Number: 63546
Gerrit-PatchSet: 5
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>
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Attention is currently required from: Andrey Petrov.
Hello build bot (Jenkins), Werner Zeh, Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63546
to look at the new patch set (#4).
Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common
......................................................................
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO).
This switches could be used in future in other CPU platforms.
Move them to common code instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not
change with this patch applied on mc_apl{1,4,5} mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/Kconfig
9 files changed, 26 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/4
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Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Gerrit-Change-Number: 63546
Gerrit-PatchSet: 4
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/d58a216b_c137e9a8
PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
There is just one bridge on this board.
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Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Gerrit-Change-Number: 63931
Gerrit-PatchSet: 2
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-Comment-Date: Mon, 02 May 2022 06:26:42 +0000
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63548
to look at the new patch set (#3).
Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
mb/siemens/mc_ehl: Disable RAPL
Disable RAPL for all mainboards based on mc_ehl.
Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.
Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Gerrit-Change-Number: 63548
Gerrit-PatchSet: 3
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Uwe Poeche.
Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63547
to look at the new patch set (#3).
Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
......................................................................
soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
Other than on previouse SOCs this needs to be done in an MCHBAR mapped
register rather than via MSR on Elkhart Lake.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/soc/intel/elkhartlake/include/soc/systemagent.h
M src/soc/intel/elkhartlake/systemagent.c
2 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63547/3
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Gerrit-Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Gerrit-Change-Number: 63547
Gerrit-PatchSet: 3
Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Uwe Poeche, Andrey Petrov.
Hello build bot (Jenkins), Werner Zeh, Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63546
to look at the new patch set (#3).
Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common
......................................................................
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO).
This switches could be used in future in other CPU platforms.
Move them to common code instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not
change with this patch applied on mc_apl{1,4,5} mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/Kconfig
9 files changed, 25 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/3
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Gerrit-Change-Number: 63546
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