coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

1 participants
6166 discussions

Change in coreboot[master]: intel/common/block: Provide RAPL and min clock ratio switches in common
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Attention is currently required from: Andrey Petrov. Hello build bot (Jenkins), Werner Zeh, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63546 to look at the new patch set (#6). Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common ...................................................................... intel/common/block: Provide RAPL and min clock ratio switches in common There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). This switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/Kconfig 9 files changed, 26 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Gerrit-Change-Number: 63546 Gerrit-PatchSet: 6 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: MAINTAINERS: Add myself as maintainer of mc_ehl boards
by Werner Zeh (Code Review) 02 May '22

02 May '22

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63778 ) Change subject: MAINTAINERS: Add myself as maintainer of mc_ehl boards ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63778/comment/458f2441_31c390b8 PS2, Line 7: MAINTAINERS: Add myself as maintainer of mc_ehl boards > Thank you for stepping up for that. […] I had a look at some previous patches of the kind and took the same syntax. Will do it like proposed the next time. -- To view, visit https://review.coreboot.org/c/coreboot/+/63778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I203f122de6641359306c2659cb9d9dc2c93d184c Gerrit-Change-Number: 63778 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 02 May 2022 06:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
by Werner Zeh (Code Review) 02 May '22

02 May '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63953 ) Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/63953/comment/e01e2db4_a9709d26 PS2, Line 801: printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); As you have the response handy here, would it make sense to show the reason for this command being failed? Or is it just another magic bitfield with no proper decoding? -- To view, visit https://review.coreboot.org/c/coreboot/+/63953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77d428f9501feaccab8bb431090d10ce8d3af9b2 Gerrit-Change-Number: 63953 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 02 May 2022 06:39:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Disable RAPL
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63548 to look at the new patch set (#5). Change subject: mb/siemens/mc_ehl: Disable RAPL ...................................................................... mb/siemens/mc_ehl: Disable RAPL Disable RAPL for all mainboards based on mc_ehl. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Gerrit-Change-Number: 63548 Gerrit-PatchSet: 5 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Attention is currently required from: Uwe Poeche. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63547 to look at the new patch set (#5). Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig ...................................................................... soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig This patch provides the possibility for EHL based boards to disable RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch. Other than on previouse SOCs this needs to be done in an MCHBAR mapped register rather than via MSR on Elkhart Lake. Test: Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1. Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/soc/intel/elkhartlake/include/soc/systemagent.h M src/soc/intel/elkhartlake/systemagent.c 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63547/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f Gerrit-Change-Number: 63547 Gerrit-PatchSet: 5 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: intel/common/block: Provide RAPL and min clock ratio switches in common
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Attention is currently required from: Andrey Petrov. Hello build bot (Jenkins), Werner Zeh, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63546 to look at the new patch set (#5). Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common ...................................................................... intel/common/block: Provide RAPL and min clock ratio switches in common There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). This switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/Kconfig 9 files changed, 26 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Gerrit-Change-Number: 63546 Gerrit-PatchSet: 5 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: intel/common/block: Provide RAPL and min clock ratio switches in common
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Attention is currently required from: Andrey Petrov. Hello build bot (Jenkins), Werner Zeh, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63546 to look at the new patch set (#4). Change subject: intel/common/block: Provide RAPL and min clock ratio switches in common ...................................................................... intel/common/block: Provide RAPL and min clock ratio switches in common There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). This switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/Kconfig 9 files changed, 26 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Gerrit-Change-Number: 63546 Gerrit-PatchSet: 4 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges
by Werner Zeh (Code Review) 02 May '22

02 May '22

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 ) Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63931/comment/d58a216b_c137e9a8 PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to There is just one bridge on this board. -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Mon, 02 May 2022 06:26:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Provide function to change PHY to MAC IRQ pola...
by Werner Zeh (Code Review) 02 May '22

02 May '22

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63888 ) Change subject: soc/intel/elkhartlake: Provide function to change PHY to MAC IRQ polarity ...................................................................... Patch Set 1: (22 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63888/comment/da395104_81e58ec5 PS1, Line 7: PHY to MAC 'PHY-to-MAC' could make things more clear here as it is the IRQ routed from the external PHY to the internal MAC which is set up here. In addition, the headline seems to be one char too long. https://review.coreboot.org/c/coreboot/+/63888/comment/7f8428b9_97dd9769 PS1, Line 9: It may be that a connected PHY requires an inverting of the interrupt : signal. Maybe: 'Based on the mainboard wiring it could be necessary to change the interrupt polarity.' File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63888/comment/abee1bd4_026f4d4e PS1, Line 246: TSN_GBE_PHY2MAC_INTR_POL Should we move to a model where the polarity is given directly instead of just 'inverting' the current one. Something like IRQ_ACTIVE_HIGH and IRQ_ACTIVE_LOW would have the benefit that the user is sure witch level is set up. https://review.coreboot.org/c/coreboot/+/63888/comment/90c3234a_49fdc481 PS1, Line 251: This invert Maybe: 'Setting this switch inverts' File src/soc/intel/elkhartlake/include/soc/tsn_gbe.h: https://review.coreboot.org/c/coreboot/+/63888/comment/f748aa11_0a8d65d5 PS1, Line 12: TSN_GMII_DELAY Add _US to the define to indicated that the timout is in microsecond units? https://review.coreboot.org/c/coreboot/+/63888/comment/3f6814dc_8888857b PS1, Line 14: ADDR Maybe 'ADR'? https://review.coreboot.org/c/coreboot/+/63888/comment/9900bf8f_37145fd5 PS1, Line 24: ADD 'ADR' as you mead address here? ADD just look weird here. https://review.coreboot.org/c/coreboot/+/63888/comment/b2a83c9a_af72cf67 PS1, Line 26: 0x40 Once you have started to use the shift syntax, why not continue here? (1 << 6) would be more consistent across the file. File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/63888/comment/0b090273_c871685f PS1, Line 34: : uint32_t i; : : for (i = 0; i < TSN_MAX_LOOP_TIME; ++i) { : if (read32((void *)(io_mem_base + TSN_MAC_MDIO_ADDR)) & TSN_MAC_GMII_BUSY) : udelay(TSN_GMII_DELAY); : else : return CB_SUCCESS; : } : printk(BIOS_ERR, "%s Timeout in %d micro seconds\n", __func__, : TSN_MAX_LOOP_TIME * TSN_GMII_DELAY); : return CB_ERR; Would it make sense to use a stopwatch here instead? You could get rid of the for-loop by just defining the overall timeout value you need. https://review.coreboot.org/c/coreboot/+/63888/comment/ee13ce3b_d61e9503 PS1, Line 48: uint8_t phy_add, uint8_t reg_add I would rather call them pyh_adr and reg_adr here. https://review.coreboot.org/c/coreboot/+/63888/comment/82bdbb85_b899a894 PS1, Line 52: Status status https://review.coreboot.org/c/coreboot/+/63888/comment/16e9be1c_263b2720 PS1, Line 55: mac_mdio_address = read32((void *)(io_mem_base + TSN_MAC_MDIO_ADDR)); : mac_mdio_address &= (uint32_t)~(TSN_MAC_MDIO_ADDR_MASK); : mac_mdio_address |= TSN_MAC_PHYAD(phy_add) | TSN_MAC_REGAD(reg_add) : | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 : | TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY; : write32((void *)(io_mem_base + TSN_MAC_MDIO_ADDR), mac_mdio_address) You could use clrsetbits() here instead, but up to you. https://review.coreboot.org/c/coreboot/+/63888/comment/49f4458e_04310a52 PS1, Line 62: // Wait for MDIO frame transfer complete before reading MDIO DATA register Please use the propper comment style here. https://review.coreboot.org/c/coreboot/+/63888/comment/4487ff89_1fc888cf PS1, Line 65: die Maybe die() is a bit to hard here. Let's try to continue as far as possible while throwing an error. https://review.coreboot.org/c/coreboot/+/63888/comment/b5e8d025_a8090cf5 PS1, Line 68: BIOS_INFO This one should be on DEBUG level (or even on SPEW) I guess, or? https://review.coreboot.org/c/coreboot/+/63888/comment/10d7be38_817ee7b2 PS1, Line 73: phy_add, uint8_t reg_add pyh_adr and reg_adr https://review.coreboot.org/c/coreboot/+/63888/comment/a1e2344b_d596d404 PS1, Line 77: Status status https://review.coreboot.org/c/coreboot/+/63888/comment/d908f80f_684888d2 PS1, Line 79: write16((void *)(io_mem_base + TSN_MAC_MDIO_DATA), mac_mdio_data); : mac_mdio_address = read32((void *)(io_mem_base + TSN_MAC_MDIO_ADDR)); : mac_mdio_address &= (uint32_t)~(TSN_MAC_MDIO_ADDR_MASK); : mac_mdio_address |= TSN_MAC_PHYAD(phy_add) | TSN_MAC_REGAD(reg_add) : | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 : | TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY; : write32((void *)(io_mem_base + TSN_MAC_MDIO_ADDR), mac_mdio_address); The same clrsetbist() commetn applies here as well. https://review.coreboot.org/c/coreboot/+/63888/comment/14bfe97e_e3906fdc PS1, Line 87: // Wait for MDIO frame transfer complete before reading MDIO DATA register Please use the proper comment style. https://review.coreboot.org/c/coreboot/+/63888/comment/67700302_fd1af9a2 PS1, Line 88: Status status https://review.coreboot.org/c/coreboot/+/63888/comment/6f71bf65_4f8f91cd PS1, Line 90: die("TSN GMII Busy. MIDO phy_add: 0x%x, Register 0x%x read invalid\n", : phy_add, reg_add); Again, die() is a bit too hard here. https://review.coreboot.org/c/coreboot/+/63888/comment/fc607a4f_ade15079 PS1, Line 93: BIOS_INFO DEBUG or even SPEW would be better here. -- To view, visit https://review.coreboot.org/c/coreboot/+/63888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Gerrit-Change-Number: 63888 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Mon, 02 May 2022 06:20:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Disable RAPL
by Uwe Poeche (Code Review) 02 May '22

02 May '22

Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63548 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl: Disable RAPL ...................................................................... mb/siemens/mc_ehl: Disable RAPL Disable RAPL for all mainboards based on mc_ehl. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Gerrit-Change-Number: 63548 Gerrit-PatchSet: 3 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2022