Hello build bot (Jenkins), Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61533
to look at the new patch set (#10).
Change subject: [only for test] test gcc-13 snapshot
......................................................................
[only for test] test gcc-13 snapshot
Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.inc
M util/crossgcc/buildgcc
D util/crossgcc/patches/gcc-11.2.0_ada-musl_workaround.patch
D util/crossgcc/patches/gcc-11.2.0_gnat.patch
D util/crossgcc/patches/gcc-11.2.0_libcpp.patch
D util/crossgcc/patches/gcc-11.2.0_libgcc.patch
R util/crossgcc/patches/gcc-13-20220501_asan_shadow_offset_callback.patch
D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum
A util/crossgcc/sum/gcc-13-20220501.tar.xz.cksum
9 files changed, 14 insertions(+), 256 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61533/10
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Gerrit-Change-Number: 61533
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Hello build bot (Jenkins), Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61533
to look at the new patch set (#9).
Change subject: [only for test] test gcc-13 snapshot
......................................................................
[only for test] test gcc-13 snapshot
Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.inc
M util/crossgcc/buildgcc
D util/crossgcc/patches/gcc-11.2.0_ada-musl_workaround.patch
D util/crossgcc/patches/gcc-11.2.0_gnat.patch
D util/crossgcc/patches/gcc-11.2.0_libcpp.patch
D util/crossgcc/patches/gcc-11.2.0_libgcc.patch
R util/crossgcc/patches/gcc-13-20220501_asan_shadow_offset_callback.patch
D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum
A util/crossgcc/sum/gcc-13-20220501.tar.xz.cksum
9 files changed, 14 insertions(+), 256 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61533/9
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63953 )
Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/63953/comment/4ab7f196_dbe3dd65
PS2, Line 801: printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n");
> OK, as assumed. Good to me then.
Thanks Werner
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63982 )
Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> The implementation looks good. However TBH, I would prefer a separate […]
Hmm. I have had the thought already to refactor it and pull out the FSPI controller from the generic SPI driver and provide a dedicated one. Not sure how others would think about it. Let me have a look how that could look like. maybe we could do this just for APL for now to see how it will be going. Moving other PCI IDs over should be easy once we have a common sense.
What do you think?
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/ebdf6f44_5ff59cce
PS1, Line 192: .acpi_hid = spi_acpi_hid,
: .acpi_name = spi_acpi_name,
> Technically, these two hooks are only useful if another driver generates […]
Yes, that's true. Will refactor in the next version.
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Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/spi/spi.c:
https://review.coreboot.org/c/coreboot/+/63982/comment/a1aa46e3_8623fe51
PS1, Line 117: spi_fill_ssdt
> Hmm don't you want to do this only when the device cannot be enumerated?
In general yes. But on APL the FSPI controller is not marked as hidden across all the boards and therefore the dev->hidden flag is not reliable. The real hidden device, which is the P2SB, is not marked as such either as during coreboot runtime it is visible and will be hidden by coreboot code before passing over to the payload.
Since it is hard coded for APL I guess assuming that FSPI is hidden is a valid assumption.
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Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/63953/comment/a1d478ce_eac94c61
PS2, Line 801: printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n");
> > As you have the response handy here, would it make sense to show the reason for this command being […]
OK, as assumed. Good to me then.
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Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> In general I think your suggestion should work, meminfo->dimm_cnt will need to be the same value as […]
But the new 'bool present' hasn't been set by all the platform codes yet, without Kconfig it seems pretty difficult to make it compatible with the current coreboot? The only optimization I can do is to move the weak function out of here into platform code.
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