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Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS6:
I think Nico just would like to know if enabling / disabling of hyper-threading works.
> As no board disabled it before, has this been tested? HT configuration at this level is not just flipping a bit, the procedure is delicate and usually involves a reboot.
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Dear All, […]
Hi Teddy,
For the SAR p-sensor device, you can only keep common_soc_config.i2c[5] related settings, but its value of parameter speed_config may also needs HW's comment to ensure the clock frequency < 400k Hz.
In addition, for register SerialIoI2cMode, could you double check the schematic to review which controller does not connected a device in schematic actually, if so, please set it to PchSerialIoDisabled.
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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
Patch Set 12: Code-Review+1
(2 comments)
File src/soc/intel/meteorlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/da510f9c_03ceda27
PS12, Line 118: report_pch_info
question: should we rename this as well from pch to soc ? or you think let it be ?
File src/soc/intel/meteorlake/bootblock/soc_die.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/bd1cf771_65153e60
PS12, Line 80: /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
: tco_configure();
note: earlier this func was called after `bootblock_soc_die_init` hence shouldn't it move under bootblock_soc_die_init now ? line #132
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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
Patch Set 12:
(6 comments)
File src/soc/intel/meteorlake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/0c804761_63672ca2
PS10, Line 20: bootblock_pch_early_init();
: ioe_p2sb_enable_bar();
: fast_spi_cache_bios_region();
: pch_early_iorange_init();
> can you please try to logically separate these functions as in […]
Done
File src/soc/intel/meteorlake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/6ea44008_e7f93395
PS11, Line 24: /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
: tco_configure();
> shouldn't TCO also should land into `bootblock_soc_die_init`?
Done
File src/soc/intel/meteorlake/bootblock/ioe_die.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/df8eae19_ec69cfe5
PS11, Line 10:
> please one newline ?
Done
File src/soc/intel/meteorlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/bf6ead2a_c8ad7985
PS11, Line 30: MeteorLake
> can we maintain the name symmetry between either MeteorLake or Meteorlake alone and not the mix?
Done
File src/soc/intel/meteorlake/bootblock/soc_die.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/a048e5a5_3a2de80e
PS11, Line 57: bootblock_systemagent_early_init();
: fast_spi_cache_bios_region();
: soc_die_early_iorange_init();
: if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
: uart_bootblock_init();
> tab please?
Done
https://review.coreboot.org/c/coreboot/+/62772/comment/52a8a004_d439d344
PS11, Line 74: Enabling PWRM Base for accessing
> Enabling SoC PMC PWRM Base for accessing
Done
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Change subject: soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62772
to look at the new patch set (#12).
Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
---
A src/soc/intel/meteorlake/Kconfig
A src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/bootblock/bootblock.c
A src/soc/intel/meteorlake/bootblock/ioe_die.c
A src/soc/intel/meteorlake/bootblock/report_platform.c
A src/soc/intel/meteorlake/bootblock/soc_die.c
A src/soc/intel/meteorlake/include/soc/bootblock.h
A src/soc/intel/meteorlake/include/soc/espi.h
A src/soc/intel/meteorlake/include/soc/iomap.h
A src/soc/intel/meteorlake/include/soc/p2sb.h
A src/soc/intel/meteorlake/include/soc/pci_devs.h
A src/soc/intel/meteorlake/include/soc/pcr_ids.h
A src/soc/intel/meteorlake/include/soc/pm.h
A src/soc/intel/meteorlake/include/soc/smbus.h
14 files changed, 1,033 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/12
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63882 )
Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> How about setting correct `meminfo->dimm_cnt` for the platforms that […]
In general I think your suggestion should work, meminfo->dimm_cnt will need to be the same value as ARRAY_SIZE(meminfo->dimm), which is set by DIMM_INFO_TOTAL, so DIMM_INFO_TOTAL will need to be a Kconfig that can be changed by platform code. The meaning of dimm_cnt will become the maximum number of DIMM supported by the SOC, not the active DIMM configuration anymore but I don't find any potential concern yet.
The weak function can be moved out of here but I think platform code will still need to let mainboard tell it if the DIMM exist on the mainboard or not.
Will try this with our private repo first and feedback.
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