Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63955 )
Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63955/comment/956c78de_2af4c932
PS2, Line 7: mb/google/brya/var/crota: update gpio configuration
:
: - set GPP_D16 to enable webcam power
> suggestion: […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
mb/google/brya/var/crota: Enable webcam power
- set GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and boot into kernel v5.10
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
---
M src/mainboard/google/brya/variants/crota/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63955/3
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Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 )
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 16:
(1 comment)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/c015a972_037da11d
PS15, Line 260: break;
> Oops. redundant. Will delete.
Done
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 15:
(3 comments)
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/2cc5af00_2d3373c1
PS12, Line 179: min_pci_d_states
> This is actually what I started with. […]
Implemented in patch set #15
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/abdb1368_56143ee0
PS13, Line 116: typedef enum {
: D0, /* 0 */
: D1, /* 1 */
: D2, /* 2 */
: D3, /* 3 */
: UNDEF
: } D_STATES;
> Ack […]
I didn't ultimately use it as it also it doesn't seem safe as it also has unsupported values (ACPI_DEVICE_SLEEP_D3_COLD).
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/7da9a236_29b8f90e
PS15, Line 260: break;
Oops. redundant. Will delete.
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Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Raj Astekar,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
---
A src/soc/intel/meteorlake/Kconfig
A src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/bootblock/bootblock.c
A src/soc/intel/meteorlake/bootblock/ioe_die.c
A src/soc/intel/meteorlake/bootblock/report_platform.c
A src/soc/intel/meteorlake/bootblock/soc_die.c
A src/soc/intel/meteorlake/include/soc/bootblock.h
A src/soc/intel/meteorlake/include/soc/espi.h
A src/soc/intel/meteorlake/include/soc/iomap.h
A src/soc/intel/meteorlake/include/soc/p2sb.h
A src/soc/intel/meteorlake/include/soc/pci_devs.h
A src/soc/intel/meteorlake/include/soc/pcr_ids.h
A src/soc/intel/meteorlake/include/soc/pm.h
A src/soc/intel/meteorlake/include/soc/smbus.h
14 files changed, 1,034 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/11
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 210 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/15
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Change subject: mb/google/corsola: Enable CBFS_VERIFICATION
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/corsola/Kconfig:
https://review.coreboot.org/c/coreboot/+/63926/comment/362f892c_1cf02479
PS5, Line 26: CBFS_VERIFICATION
> Should we move this to config config VBOOT, or maybe "select CBFS_VERIFICATION if VBOOT"? […]
Sorry, this shouldn't be here at all. It's a user decision, not describing the hardware. So we should add it in the coreboot ebuild config file. (Idk if we have a ti50 USE flag... if we do, maybe the ebuild could add this automatically based on that rather than having to add it to each individual config.<board> file.)
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Change subject: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Patchset:
PS1:
> (oh, was that because romstages should never return - only jump directly to ramstage?)
Yes, basically you can only overlap regions that are never needed at the same time (with the consideration that a region is also "needed" by the stage that loads code into it). The bootblock does load the romstage in a !VBOOT scenario, but the romstage doesn't return to the bootblock, so once you're in romstage you can overwrite the bootblock with DRAM init code.
> 3. Use `OVERLAP_VERSTAGE_ROMSTAGE` instead of `OVERLAP_DECOMPRESSOR_*`
Well, there's no difference between those two macros when COMPRESS_BOOTBLOCK is not enabled. On the other hand you should always try enabling COMPRESS_BOOTBLOCK unless you've already confirmed that it doesn't provide a benefit for your platform (when measuring that, keep in mind that boot ROM loading usually do not show up in timestamps... you'll need to check with a SPI analyzer). But that's not related to this patch.
File src/soc/mediatek/mt8186/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/63924/comment/e174957f_8b2152bb
PS2, Line 25: TTB(0x00100000, 28K)
: DMA_COHERENT(0x00107000, 4K)
: TPM_TCPA_LOG(0x00108000, 2K)
: FMAP_CACHE(0x00108800, 2K)
: WATCHDOG_TOMBSTONE(0x00109000, 4)
: CBFS_MCACHE(0x00109004, 16K - 4)
: /* EMPTY(0x0010d000, 4K) */
: STACK(0x0010E000, 7K)
: TIMESTAMP(0x0010FC00, 1K)
: /* MT8186 has 64KB SRAM. */
> I think you are right. […]
Yes, that's a good point, it would be good if you could add an extra assertion to the STACK() macro. Both base and size should be divisible by 16 (AArch64 ABI requires SP to be 16-byte aligned between function calls).
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