Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63944 )
Change subject: commonlib/mem_chip_info: Add clarifying documentation comments
......................................................................
commonlib/mem_chip_info: Add clarifying documentation comments
This patch just adds some comments to the recently merged mem_chip_info
struct for communicating memory type information to the payload/OS, to
clarify the expected format in which values are to be written into the
fields.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I2c28b3bdcdb13b7f270fb87a8f06e2cf448cddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63944
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shelley Chen <shchen(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Shelley Chen: Looks good to me, approved
diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
index d07f4d6..0d92b52 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
@@ -14,16 +14,16 @@
};
struct mem_chip_info {
- uint8_t type; /* enum mem_chip_type */
+ uint8_t type; /* enum mem_chip_type */
uint8_t num_channels;
uint8_t reserved[6];
struct mem_chip_channel {
- uint64_t density;
- uint8_t io_width;
- uint8_t manufacturer_id;
- uint8_t revision_id[2];
+ uint64_t density; /* number in _bytes_, not Megabytes! */
+ uint8_t io_width; /* should be `8`, `16`, `32` or `64` */
+ uint8_t manufacturer_id; /* raw value from MR5 */
+ uint8_t revision_id[2]; /* raw values from MR6 and MR7 */
uint8_t reserved[4];
- uint8_t serial_id[8]; /* LPDDR5 only */
+ uint8_t serial_id[8]; /* LPDDR5 only, MR47 - MR54 */
} channel[0];
};
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63944 )
Change subject: commonlib/mem_chip_info: Add clarifying documentation comments
......................................................................
Patch Set 2:
(3 comments)
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/63944/comment/24634abe_145b7654
PS2, Line 18: uint8_t num_channels;
> Out of curiosity, is it required to specify the size of the members, or coud `unsigned int` be used […]
Yes, this structure is meant to be serialized in the coreboot table, fixed width is important.
https://review.coreboot.org/c/coreboot/+/63944/comment/e3971982_0ca66f49
PS2, Line 21: uint64_t density; /* number in _bytes_, not Megabytes! */
> Should the unit be appended to the name?
The name is already being used in payload code so a bit too much of a pain to change right now... also matches existing LPDDR spec usage.
https://review.coreboot.org/c/coreboot/+/63944/comment/641d8fdc_0cc49b77
PS2, Line 23: uint8_t manufacturer_id; /* raw value from MR5 */
> Should a tab be used here too?
No, because then it's even further to the right. I want the comments to all start on the same column but I also didn't want to add yet another tab everywhere because then it gets too tight, so this was the compromise.
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63774 )
Change subject: lib/spd: Demote log about using default DDR4 params to NOTICE
......................................................................
Patch Set 5: Code-Review+1
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Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/corsola: Enable CBFS_VERIFICATION
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/corsola/Kconfig:
https://review.coreboot.org/c/coreboot/+/63926/comment/3db35be5_cff4db76
PS5, Line 26: CBFS_VERIFICATION
Should we move this to config config VBOOT, or maybe "select CBFS_VERIFICATION if VBOOT"?
Did it work when you select from overlay configs?
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Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> Let's summarize what we can try: […]
Yes that's things we can try. but it's totally fine to try them in follow up changes. Let's merge your version now to unblock CBFS verification development.
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Change subject: mb/google/brya/acpi: Add support for NBCI _DSM subfunction
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/mainboard/google/brya/acpi/nbci.asl:
https://review.coreboot.org/c/coreboot/+/64008/comment/6907f65e_369f51d4
PS1, Line 25: (0 << 10) | /* No 3D Hotkeys */
is it like `10` is to represent bit10 and `0` to represent `no`?
likewise other bits like bit 9, bit 7 etc.?
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#14).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/common/block/acpi/pep.c
4 files changed, 416 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/14
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