coreboot-gerrit May 2022

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Change in coreboot[master]: lenovo: correct typo in macro H8_HAS_BAT_THRESHOLDS_IMPL
by Felix Singer (Code Review) 03 May '22

03 May '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63991 ) Change subject: lenovo: correct typo in macro H8_HAS_BAT_THRESHOLDS_IMPL ...................................................................... lenovo: correct typo in macro H8_HAS_BAT_THRESHOLDS_IMPL Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: Ia0550a115d75183cd72e478ae739731001febe22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63991 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/acpi/thinkpad.asl M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/w541/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig 17 files changed, 17 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 2ea4faa9..698816f 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -28,7 +28,7 @@ Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot. -config H8_HAS_BAT_TRESHOLDS_IMPL +config H8_HAS_BAT_THRESHOLDS_IMPL bool default n diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 48e76dc..23c1e02 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -304,7 +304,7 @@ } } - #if CONFIG(H8_HAS_BAT_TRESHOLDS_IMPL) + #if CONFIG(H8_HAS_BAT_THRESHOLDS_IMPL) #include "thinkpad_bat_thresholds.asl" #endif } diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 8c53a68..f90ed53 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -9,7 +9,7 @@ select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index cff8769..3495d66 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -20,7 +20,7 @@ select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_RICOH_RCE822 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 553438f..b82f45a 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 1f715fd..2732d86 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 64a73f3..449f5c1 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select DRIVERS_RICOH_RCE822 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select EC_LENOVO_PMH7 select NO_UART_ON_SUPERIO select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index fe5b895..373d08f 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 6c4f7b0..4e14907 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select EC_LENOVO_H8 select EC_LENOVO_PMH7 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index ecd9aa9..81a1e30d 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -6,7 +6,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b3b0989..7420617 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -6,7 +6,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig index 81a3b85..507de1a 100644 --- a/src/mainboard/lenovo/w541/Kconfig +++ b/src/mainboard/lenovo/w541/Kconfig @@ -5,7 +5,7 @@ select BOARD_ROMSIZE_KB_12288 select EC_LENOVO_H8 select EC_LENOVO_PMH7 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index f514e7c..281f6b0b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index b4d677a..812ceee 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 6c174c5..abc2352 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -21,7 +21,7 @@ select MAINBOARD_HAS_TPM1 select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index d4b5bca..97ad1ac 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -7,7 +7,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index a6fd796..f966726 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,7 +8,7 @@ select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_BAT_THRESHOLDS_IMPL select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0550a115d75183cd72e478ae739731001febe22 Gerrit-Change-Number: 63991 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
by Subrata Banik (Code Review) 03 May '22

03 May '22

Attention is currently required from: Felix Singer, Nico Huber, Tim Wawrzynczak, Michael Niewöhner. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60547 ) Change subject: soc/intel/alderlake: Hook up FSP hyper-threading setting to option API ...................................................................... Patch Set 11: (1 comment) Patchset: PS6: > haha you're not wrong 😜 yes UPD tried to override the CPU softstrap for hyperthreading hence, results into an additional reboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/60547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce Gerrit-Change-Number: 60547 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 03 May 2022 19:40:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/release: Update genrelnotes with the latest version
by Felix Held (Code Review) 03 May '22

03 May '22

Attention is currently required from: Martin L Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62440 ) Change subject: util/release: Update genrelnotes with the latest version ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62440/comment/8b53a222_a6bb09f3 PS3, Line 13: messages one double space and one missing space -- To view, visit https://review.coreboot.org/c/coreboot/+/62440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4 Gerrit-Change-Number: 62440 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 19:39:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/infra/builders.md: Fix markdown inssues
by Felix Held (Code Review) 03 May '22

03 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63804 ) Change subject: Documentation/infra/builders.md: Fix markdown inssues ...................................................................... Documentation/infra/builders.md: Fix markdown inssues This fixes the following issues found by the markdown lint tool, mdl: MD014 Dollar signs used before commands without showing output MD026 Trailing punctuation in header MD030 Spaces after list markers MD031 Fenced code blocks should be surrounded by blank lines MD040 Fenced code blocks should have a language specified Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I82317f51c003b2c23d64c3cbbcecbf9a39d5d509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/infrastructure/builders.md 1 file changed, 55 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md index 0c3e99c..b5d7775 100644 --- a/Documentation/infrastructure/builders.md +++ b/Documentation/infrastructure/builders.md @@ -46,20 +46,20 @@ These times are taken from the week of Feb 21 - Feb 28, 2022 * Congenialbuilder - 128 threads, 256GiB RAM - * Fastest Passing coreboot gerrit build: 6 min, 47 sec - * Slowest Passing coreboot gerrit build: 14 min + * Fastest Passing coreboot gerrit build: 6 min, 47 sec + * Slowest Passing coreboot gerrit build: 14 min -* Gleefulbuilder - 64 thread, 64GiB RAM - * Fastest Passing coreboot gerrit build: 10 min - * Slowest Passing coreboot gerrit build: 46 min +* Gleefulbuilder - 64 threads, 64GiB RAM + * Fastest Passing coreboot gerrit build: 10 min + * Slowest Passing coreboot gerrit build: 46 min * Fabulousbuilder - 64 threads, 64GiB RAM - * Fastest Passing coreboot gerrit build: 7 min, 56 sec - * Slowest Passing coreboot gerrit build: 56 min (No ccache) + * Fastest Passing coreboot gerrit build: 7 min, 56 sec + * Slowest Passing coreboot gerrit build: 56 min (No ccache) * Ultron (9elements) - 48 threads, 128GiB RAM - * Fastest Passing coreboot gerrit build: 12 - * Slowest Passing coreboot gerrit build: 58 min + * Fastest Passing coreboot gerrit build: 12 + * Slowest Passing coreboot gerrit build: 58 min ### Jenkins Builds @@ -75,11 +75,11 @@ Most of the time on the builders is taken up by the coreboot master and coreboot gerrit builds. -* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +*[coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) -* [coreboot master build](https://qa.coreboot.org/job/coreboot/) +*[coreboot master build](https://qa.coreboot.org/job/coreboot/) ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) @@ -91,8 +91,8 @@ On a system with 32 cores, it was tested with this command: -``` -$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +```sh +stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m ``` You can watch the temperature with the sensors package or with ‘acpi -t’ @@ -102,8 +102,8 @@ if the values go down on any of the cores after it's been running for a while. -``` -$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +```sh +while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done ``` If the machine throttles or resets, you probably need to upgrade the @@ -142,7 +142,7 @@ As a regular user - *Not root*, run: -``` +```sh sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} @@ -158,7 +158,7 @@ your shell's .rc file. Note that you only need to set them if you're using something other than the default. -``` +```sh # Set the port used on your machine to connect to jenkins. export COREBOOT_JENKINS_PORT=49151 @@ -180,13 +180,13 @@ From the coreboot directory, run -``` +```sh make -C util/docker help ``` This will show you the available targets and variables needed: -``` +```text Commands for working with docker images: coreboot-sdk - Build coreboot-sdk container upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com @@ -221,7 +221,7 @@ ### Install the coreboot jenkins builder -``` +```sh make -C util/docker docker-jenkins-server ``` @@ -252,11 +252,12 @@ ### How to log in to the docker instance for debugging -``` - $ make -C util/docker docker-jenkins-attach - $ su coreboot - $ cd ~/slave-root/workspace - $ bash + +```sh +make -C util/docker docker-jenkins-attach +su coreboot +cd ~/slave-root/workspace +bash ``` @@ -273,18 +274,18 @@ To delete the old containers & images: -``` -$ docker stop $COREBOOT_JENKINS_CONTAINER -$ docker rm $COREBOOT_JENKINS_CONTAINER -$ docker images # lists all existing images -$ docker rmi XXXX # Use the image ID found in the above command. +```sh +docker stop $COREBOOT_JENKINS_CONTAINER +docker rm $COREBOOT_JENKINS_CONTAINER +docker images # lists all existing images +docker rmi XXXX # Use the image ID found in the above command. ``` To get and run the new coreboot-jenkins image, change the value in the `DOCKER_COMMIT` variable to the new image value. -``` -$ make -C util/docker docker-jenkins-server +```sh +make -C util/docker docker-jenkins-server ``` #### Getting ready to push the docker images @@ -298,15 +299,15 @@ Make sure your credentials are configured on your host machine by running -``` -$ docker login +```sh +docker login ``` This will prompt you for your docker username, password, and your email address, and write out to ~/.docker/config.json. Without this file, you won’t be able to push the images. -#### Updating the Dockerfiles: +#### Updating the Dockerfiles The coreboot-sdk Dockerfile will need to be updated when any additional dependencies are added. Both the coreboot-sdk and the @@ -317,15 +318,15 @@ Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) page before updating the files. -#### Rebuilding the coreboot-sdk docker image to update the toolchain: +#### Rebuilding the coreboot-sdk docker image to update the toolchain -``` -$ make -C util/docker coreboot-sdk +```sh +make -C util/docker coreboot-sdk ``` This takes a relatively long time. -#### Test the coreboot-sdk docker image: +#### Test the coreboot-sdk docker image There are two methods of running the docker image - interactively as a shell, or doing the build directly. Running interactively as a shell is @@ -333,44 +334,44 @@ (without any changes getting saved) and re-test builds. This saves the time of having to rebuild the image for every issue you find. -#### Running the docker image interactively: +#### Running the docker image interactively Run: -``` -$ make -C util/docker docker-jenkins-server -$ make -C util/docker docker-jenkins-attach +```sh +make -C util/docker docker-jenkins-server +make -C util/docker docker-jenkins-attach ``` -#### Running the build directly: +#### Running the build directly From the coreboot directory: -``` -$ make -C util/docker docker-build-coreboot +```sh +make -C util/docker docker-build-coreboot ``` You’ll also want to test building the other projects and payloads: ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, nvramcui, tint... -#### Pushing the coreboot-sdk image to hub.docker.com for use: +#### Pushing the coreboot-sdk image to hub.docker.com for use When you’re satisfied with the testing, push the coreboot-sdk image to the hub.docker.com -``` -$ make -C util/docker upload-coreboot-sdk +```sh +make -C util/docker upload-coreboot-sdk ``` -#### Building and pushing the coreboot-jenkins-node docker image: +#### Building and pushing the coreboot-jenkins-node docker image This docker image is pretty simple, so there’s not really any testing that needs to be done. -``` -$ make -C util/docker coreboot-jenkins-node -$ make -C util/docker upload-coreboot-jenkins-node +```sh +make -C util/docker coreboot-jenkins-node +make -C util/docker upload-coreboot-jenkins-node ``` ### Coverity Setup @@ -391,7 +392,7 @@ (cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a symlink: -``` +```sh ln -s cov-analysis-linux64-7.7.0.4 coverity ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82317f51c003b2c23d64c3cbbcecbf9a39d5d509 Gerrit-Change-Number: 63804 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
by Felix Held (Code Review) 03 May '22

03 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63457 ) Change subject: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks ...................................................................... soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and CLKREQ signals. ADL-S CPUs do not have Thunderbolt. Based on the Intel DOC #619501 and #619362. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4ab58d4..1507d6f2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -212,16 +212,17 @@ default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P + default 28 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 0 if SOC_INTEL_ALDERLAKE_PCH_N - default 3 if SOC_INTEL_ALDERLAKE_PCH_P + default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S config MAX_TBT_ROOT_PORTS int - default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S default 2 if SOC_INTEL_ALDERLAKE_PCH_M default 4 if SOC_INTEL_ALDERLAKE_PCH_P @@ -234,12 +235,14 @@ default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 7 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config SMM_TSEG_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/63457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Gerrit-Change-Number: 63457 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intelblocks/pep: Handle TBT displays on s0ix transition
by Felix Held (Code Review) 03 May '22

03 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63980 ) Change subject: intelblocks/pep: Handle TBT displays on s0ix transition ...................................................................... intelblocks/pep: Handle TBT displays on s0ix transition Notify IOM to enable or disable TBT displays on S0ix exit and entry respectively. Change-Id: I9f49d8e30fe8e8b335128e53d71ef902328f031a Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63980 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Krystian Hebel: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 1399438..8028b81 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -17,6 +17,8 @@ #define MAINBOARD_DISPLAY_HOOK "\\_SB.MDSX" #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" +#define THUNDERBOLT_DEVICE "\\_SB.PCI0.TXHC" +#define THUNDERBOLT_IOM_DPOF "\\_SB.PCI0.DPOF" #define LPI_STATES_ALL 0xff #define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0 #define PEPD_SCOPE "\\_SB.PCI0" @@ -129,6 +131,11 @@ acpigen_write_if_cond_ref_of(ENABLE_PM_BITS_HOOK); acpigen_emit_namestring(ENABLE_PM_BITS_HOOK); acpigen_write_if_end(); + + /* Handle Thunderbolt displays */ + acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE); + acpigen_write_store_int_to_namestr(1, THUNDERBOLT_IOM_DPOF); + acpigen_write_if_end(); } static void lpi_s0ix_exit(void *unused) @@ -149,6 +156,11 @@ acpigen_write_if_cond_ref_of(RESTORE_PM_BITS_HOOK); acpigen_emit_namestring(RESTORE_PM_BITS_HOOK); acpigen_write_if_end(); + + /* Handle Thunderbolt displays */ + acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE); + acpigen_write_store_int_to_namestr(0, THUNDERBOLT_IOM_DPOF); + acpigen_write_if_end(); } static void lpi_display_on(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/63980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f49d8e30fe8e8b335128e53d71ef902328f031a Gerrit-Change-Number: 63980 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intelblocks/pep: Add display on/off notifications
by Felix Held (Code Review) 03 May '22

03 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62494 ) Change subject: intelblocks/pep: Add display on/off notifications ...................................................................... intelblocks/pep: Add display on/off notifications Add display on and off notifications which call mainboard hooks if present. This allows to handle some board specific functions in user absence or presence (when display goes off from inactivity or on from activity). TEST=Use Display on/off notification on Clevo NV41 to tell EC about laptop inactivity. It is necessary to properly handle S0ix entry (stop the fans and start blinking the power led). Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Krystian Hebel: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index b83b714..1399438 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -14,6 +14,7 @@ #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" #define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" #define MAINBOARD_HOOK "\\_SB.MS0X" +#define MAINBOARD_DISPLAY_HOOK "\\_SB.MDSX" #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" #define LPI_STATES_ALL 0xff @@ -150,12 +151,30 @@ acpigen_write_if_end(); } +static void lpi_display_on(void *unused) +{ + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK); + acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); +} + +static void lpi_display_off(void *unused) +{ + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK); + acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); +} + static void (*lpi_s0_helpers[])(void *) = { NULL, /* enumerate functions (autogenerated) */ lpi_get_constraints, /* get device constraints */ NULL, /* get crash dump device */ - NULL, /* display off notify */ - NULL, /* display on notify */ + lpi_display_off, /* display off notify */ + lpi_display_on, /* display on notify */ lpi_s0ix_entry, /* s0ix entry */ lpi_s0ix_exit, /* s0ix exit */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Gerrit-Change-Number: 62494 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intelblocks/pep: Add display on/off notifications
by Felix Held (Code Review) 03 May '22

03 May '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62494 ) Change subject: intelblocks/pep: Add display on/off notifications ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62494/comment/c30211ab_359499a3 PS3, Line 8: : Add display on and off notifications which call mainboard hooks if : present. This allows to handle some board specific functions in user : absence or presence (whe ndisplay goes off from inactivity or on from : activity). : : Additionally notify IOM to enable or disable TBT displays on S0ix : exit and entry respectively. > Moved TBT related changes to CB:63980 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Gerrit-Change-Number: 62494 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 03 May 2022 19:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Fix wrong typec_port for voxel
by Tim Wawrzynczak (Code Review) 03 May '22

03 May '22

Attention is currently required from: Nick Vaccaro, Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64022 ) Change subject: mb/google/volteer: Fix wrong typec_port for voxel ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Ooh, that's a good catch, would you mind filing a different bug for this Derek? Nick, this will need to end up in the volteer firmware branch, make sure to add the voxel TAM to the bug to let them know -- To view, visit https://review.coreboot.org/c/coreboot/+/64022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f Gerrit-Change-Number: 64022 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 May 2022 19:28:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add support for catching null dereferences through debug regs
by Tim Wawrzynczak (Code Review) 03 May '22

03 May '22

Attention is currently required from: Robert Zieba, Raul Rangel, Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Tim Wawrzynczak, Kyösti Mälkki, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63657 ) Change subject: arch/x86: Add support for catching null dereferences through debug regs ...................................................................... Patch Set 11: Code-Review+1 (2 comments) File src/arch/x86/null_breakpoint.c: https://review.coreboot.org/c/coreboot/+/63657/comment/2518cadb_1e86e4ea PS11, Line 19: nit: extra tab https://review.coreboot.org/c/coreboot/+/63657/comment/1ef4c2a9_fd9ae931 PS11, Line 21: nit: extra tab -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 11 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 19:25:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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