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Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/63367/comment/3770c07e_ca78b82e
PS1, Line 10: MSR_VR_MISC_CONFIG2
> Hmmm, I guess this MSR only exists on platforms with FIVR? If so, I'd expect TGL to have this MSR as […]
Oh yeah, I don't see it in the TGL EDS... I know that Intel keeps reconfiguring the FIVR support, but TGL was all-in IIRC.
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/ec/starlabs/merlin/variants/cezanne/emem.asl:
https://review.coreboot.org/c/coreboot/+/62994/comment/1f62b2be_2675621d
PS4, Line 138: Offset(0xf7),
: TBTC, 8, // Thunderbolt Command
: TBTP, 8, // Thunderbolt Data Port
: TBTD, 8, // Thunderbolt Data
: TBTA, 8, // Thunderbolt Acknowledge
: TBTG, 16, // Thunderbolt DBG Data
> They share the same EC code as the Intel ones - so I guess these are just "Reserved but added for co […]
If possible (i.e. if it doesn't cause errors), I wouldn't define these fields. If not, I'd add a comment about it.
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Change subject: soc/intel/alderlake/pmc_descriptor.c: Don't depend on FMAP
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/bootblock/pmc_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63141/comment/b99c6208_6c068c54
PS2, Line 62: if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0)
: return;
> I would probably keep this as the first early return?
+1
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Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/63367/comment/e46f2f64_03f78368
PS1, Line 10: MSR_VR_MISC_CONFIG2
> > Yeah I see it defined in the EDS, but FSP does not program it, and neither does coreboot. […]
Hmmm, I guess this MSR only exists on platforms with FIVR? If so, I'd expect TGL to have this MSR as well.
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Change subject: libpayload/defconfig: enable vboot Lib Build
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63240/comment/c7c6799f_b4b118fb
PS3, Line 9: #3461454
can you make this a link, e.g.
`https://crrev.com/c/3461454`
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Change subject: ChromeOS: Promote variant_cros_gpio()
......................................................................
Patch Set 17:
(1 comment)
File src/vendorcode/google/chromeos/chromeos.h:
https://review.coreboot.org/c/coreboot/+/58897/comment/fcfd7c97_de658c57
PS17, Line 100: variant_cros_gpios
> It's currently defined at variant-scope in most cases
Yes, but just it feels odd to have a common, visible-outside-mainboard-scope function prefixed with `variant_` :shrug
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Change subject: ChromeOS: Promote variant_cros_gpio()
......................................................................
Patch Set 17:
(1 comment)
File src/vendorcode/google/chromeos/chromeos.h:
https://review.coreboot.org/c/coreboot/+/58897/comment/45e09451_0577f3f2
PS17, Line 100: variant_cros_gpios
> suggestion: now in maybe another patch, a better name might be […]
It's currently defined at variant-scope in most cases
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