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Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 616 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/5
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/bootblock/update_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63365/comment/e3eb58f2_ae7633a3
PS5, Line 42: CONFIG_SI_DESC_REGION_SZ
re: these Kconfigs, see https://review.coreboot.org/c/coreboot/+/63139
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Attention is currently required from: Michał Żygowski, Stefan Reinauer.
Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63374
to look at the new patch set (#4).
Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 616 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/4
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Change subject: mb/google/brya/var/nereid: Enable pen garage
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
did you also test wake from S0ix?
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Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/63367/comment/47f9775a_5534a7b3
PS1, Line 10: MSR_VR_MISC_CONFIG2
> i could see this MSR defined for ADL Alder Lake P Processor […]
Yeah I see it defined in the EDS, but FSP does not program it, and neither does coreboot.
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Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63374
to look at the new patch set (#3).
Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 606 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/3
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Hello Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63374
to look at the new patch set (#2).
Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 601 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/2
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Jett Rink has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/63158 )
Change subject: tpm: Accept Google Ti50 TPM DID:VID
......................................................................
Removed Code-Review+1 by Jett Rink <jettrink(a)google.com>
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Change subject: Makefile.inc: Add the x86 bootblock as a regular cbfs file
......................................................................
Patch Set 9:
(1 comment)
File src/arch/x86/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/56122/comment/0d3ee911_9cfe0e37
PS9, Line 107: bootblock-options := $(TS_OPTIONS) $(TXTIBB)
> Can't we just put the -b here as well (maybe if you use = instead of := )? Or is there no way to make the whole Makefile evaluation order work out with that? Hardcoding this special case into cbfs-add-to-region is pretty ugly (and honestly, if the bootblock needs to be so special that it needs a hardcoded special case in there, maybe it shouldn't be using the cbfs-files framework after all?).
I've tried a lot of things but it never works. The position argument is evaluated too early. I'll add an intermediate target.
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