coreboot-gerrit April 2022

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Change in coreboot[master]: demo: combo
by Bao Zheng (Code Review) 01 Apr '22

01 Apr '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63292 ) Change subject: demo: combo ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f51fab065ad566be4d01b78d37455b0e61bd284 Gerrit-Change-Number: 63292 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: amdfwtool: Add APCB combo
by Bao Zheng (Code Review) 01 Apr '22

01 Apr '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58620 ) Change subject: amdfwtool: Add APCB combo ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c2bf7d98ded43848ae8a8bb61d1ded1a277f88 Gerrit-Change-Number: 58620 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: amdfwtool: Move PSP padding into a loop for combo
by Bao Zheng (Code Review) 01 Apr '22

01 Apr '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58554 ) Change subject: amdfwtool: Move PSP padding into a loop for combo ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d Gerrit-Change-Number: 58554 Gerrit-PatchSet: 21 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: amdfwtool: Create & fill the combo header and write to EFS header
by Bao Zheng (Code Review) 01 Apr '22

01 Apr '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55412 ) Change subject: amdfwtool: Create & fill the combo header and write to EFS header ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3d831c7764ac4625b336d40e09bb308d339f7b Gerrit-Change-Number: 55412 Gerrit-PatchSet: 28 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: amdfwtool: Put soc name setting to fw.cfg from command line
by Bao Zheng (Code Review) 01 Apr '22

01 Apr '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58552 ) Change subject: amdfwtool: Put soc name setting to fw.cfg from command line ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Gerrit-Change-Number: 58552 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/brya: Disable PCH USB2 phy power gating ...................................................................... mb/google/brya: Disable PCH USB2 phy power gating The patch disables PCH USB2 Phy power gating. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63294/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index f2276d0..a110f98 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -22,6 +22,9 @@ # Enable CNVi BT register "cnvi_bt_core" = "true" + # Disable PCH USB2 Phy power gating + register "usb2_phy_sus_pg_disable" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable PCH USB2 Phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Enable PCH USB2 Phy power gating ...................................................................... soc/intel/alderlake: Enable PCH USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from devicetree. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a69e645..e82f2e4 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -566,6 +566,12 @@ * Default 0. Set this to 1 in order to disable C state demotion. */ bool disable_c1_state_auto_demotion; + + /* + * Enable PCH USB2 Phy power gating. + * Default 0. Set this to 1 in orderto disable PCH USB2 Phy Power gating. + */ + bool usb2_phy_sus_pg_disable; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd2c0be..5c94f39 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -499,6 +499,8 @@ if (config->tcss_ports[i].enable) s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } + + s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; } static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz
by Eddy Lu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel. Eddy Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63241 ) Change subject: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63241/comment/87504550_211d543e PS1, Line 2: eddylu(a)ami.corp-partner.google.com > Please fix: […] Done https://review.coreboot.org/c/coreboot/+/63241/comment/1428ad8b_126d691b PS1, Line 7: mb/google/brya/var/vell: Adjust I2C speed > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/63241/comment/3e9932f4_58fa1ddc PS1, Line 16: eddylu(a)ami.corp-partner.google.com > Can you change your `user. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Gerrit-Change-Number: 63241 Gerrit-PatchSet: 2 Gerrit-Owner: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Reviewer: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <coreboot.test(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 05:18:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz
by Eddy Lu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: YH Lin, Eddy Lu. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63241 to look at the new patch set (#2). Change subject: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz ...................................................................... mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu(a)ami.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63241/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Gerrit-Change-Number: 63241 Gerrit-PatchSet: 2 Gerrit-Owner: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <coreboot.test(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N
by Reka Norman (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: V Sowmya, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Usha P. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62913 ) Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Gerrit-Change-Number: 62913 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 05:12:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022