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Change subject: ChromeOS: Add DECLARE_x_CROS_GPIOS()
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS4:
> I do not like the function part of this either, let me find another way.
This is much better!
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Change subject: ChromeOS: Promote variant_cros_gpio()
......................................................................
Patch Set 17: Code-Review+2
(2 comments)
Patchset:
PS17:
Nice! This removes the common->mainboard->common code jump that the old path went through 😊
File src/vendorcode/google/chromeos/chromeos.h:
https://review.coreboot.org/c/coreboot/+/58897/comment/80b39527_7c44a84e
PS17, Line 100: variant_cros_gpios
suggestion: now in maybe another patch, a better name might be
`mainboard_cros_gpios()`
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Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/63367/comment/f75d48d4_6a2dcb37
PS1, Line 10: MSR_VR_MISC_CONFIG2
> Yeah I see it defined in the EDS, but FSP does not program it, and neither does coreboot.
Yes, for that, the commit msg need to be updated to reflect the same "The `MSR_VR_MISC_CONFIG2` was copy-pasted from Haswell/Broadwell code, but newer processors never used MSR 0x636, hence dropping with this code change".
"newer processors don't have this MSR." => I read this as EDS doesn't have this MSR defined.
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Change subject: ChromeOS: Drop filling ECFW_RW/RO state in CNVS
......................................................................
Patch Set 3: Code-Review+2
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Hello build bot (Jenkins), Michał Żygowski, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
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Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 616 insertions(+), 0 deletions(-)
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/bootblock/update_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63365/comment/e3eb58f2_ae7633a3
PS5, Line 42: CONFIG_SI_DESC_REGION_SZ
re: these Kconfigs, see https://review.coreboot.org/c/coreboot/+/63139
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Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
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---
M util/inteltool/gpio.c
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A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 616 insertions(+), 0 deletions(-)
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Change subject: mb/google/brya/var/nereid: Enable pen garage
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
did you also test wake from S0ix?
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Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/63367/comment/47f9775a_5534a7b3
PS1, Line 10: MSR_VR_MISC_CONFIG2
> i could see this MSR defined for ADL Alder Lake P Processor […]
Yeah I see it defined in the EDS, but FSP does not program it, and neither does coreboot.
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
TEST: dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 606 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/3
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