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Change subject: soc/intel/apl: Write to cbfs regions using intermediate targets
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63224/comment/2972ef68_77fe90bd
PS4, Line 9: There is no need to
There is no need to ...? Something is missing in this sentence
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Change subject: amdfwtool: Change the name of macros for 'BHD'
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Patch Set 26: Code-Review+1
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/9719cbd7_4dedfee5
PS2, Line 620: /* UFS */
> ADL-P/N/M PCH, I see this in the PCH HAS.
Hi Meera, I checked the EDS, seems like UFS on both ADL have only 1 port, but 2 lanes? So i presume that the UfsEnable[] is referring to port, not lane?
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Change subject: mb/google/brya/var/nereid: Add WLAN power sequence
......................................................................
Patch Set 2: Code-Review+2
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Change subject: tpm: Accept Google Ti50 TPM DID:VID
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/volteer/.history_*outside*:
PS12:
Is this meant to be committed?
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62994/comment/34611861_9baa217c
PS4, Line 10: "Fighter
> nit: missing closing "
Done
File src/ec/starlabs/merlin/variants/cezanne/emem.asl:
https://review.coreboot.org/c/coreboot/+/62994/comment/836b440b_7b9813e9
PS4, Line 138: Offset(0xf7),
: TBTC, 8, // Thunderbolt Command
: TBTP, 8, // Thunderbolt Data Port
: TBTD, 8, // Thunderbolt Data
: TBTA, 8, // Thunderbolt Acknowledge
: TBTG, 16, // Thunderbolt DBG Data
> Thunderbolt on AMD systems?
They share the same EC code as the Intel ones - so I guess these are just "Reserved but added for completeness"
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62994
to look at the new patch set (#5).
Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
......................................................................
ec/starlabs/merlin: Add EC related files for Cezanne boards
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
---
A src/ec/starlabs/merlin/variants/cezanne/ecdefs.h
A src/ec/starlabs/merlin/variants/cezanne/emem.asl
A src/ec/starlabs/merlin/variants/cezanne/events.asl
3 files changed, 360 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62994/5
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