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Change subject: tpm: Accept Google Ti50 TPM DID:VID
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/volteer/.history_*outside*:
PS12:
Is this meant to be committed?
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62994/comment/34611861_9baa217c
PS4, Line 10: "Fighter
> nit: missing closing "
Done
File src/ec/starlabs/merlin/variants/cezanne/emem.asl:
https://review.coreboot.org/c/coreboot/+/62994/comment/836b440b_7b9813e9
PS4, Line 138: Offset(0xf7),
: TBTC, 8, // Thunderbolt Command
: TBTP, 8, // Thunderbolt Data Port
: TBTD, 8, // Thunderbolt Data
: TBTA, 8, // Thunderbolt Acknowledge
: TBTG, 16, // Thunderbolt DBG Data
> Thunderbolt on AMD systems?
They share the same EC code as the Intel ones - so I guess these are just "Reserved but added for completeness"
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I'd like you to reexamine a change. Please visit
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
......................................................................
ec/starlabs/merlin: Add EC related files for Cezanne boards
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
---
A src/ec/starlabs/merlin/variants/cezanne/ecdefs.h
A src/ec/starlabs/merlin/variants/cezanne/emem.asl
A src/ec/starlabs/merlin/variants/cezanne/events.asl
3 files changed, 360 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62994/5
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/starlabs/labtop: Add LabTop Mk III
......................................................................
Patch Set 75:
(1 comment)
This change is ready for review.
Patchset:
PS75:
> Looks good, any reason why it's WIP?
Snuck in a GPIO change - wanted to make sure the world didn't end!
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/63365/comment/7e618020_5e38835f
PS4, Line 20: void configure_pmc_descriptor(void);
> Yeah, Sridhar would you mind doing this? Then I'll update my change.
Done.
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Change subject: mb/google/brya/var/nereid: Add WLAN power sequence
......................................................................
mb/google/brya/var/nereid: Add WLAN power sequence
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
in S3.
- During warm reboot, if we only assert RST without pulling the power
low, then the kernel crashes.
As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low and high again in bootblock to make
sure it goes low during warm reboot.
BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.
Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/mainboard/google/brya/variants/nereid/gpio.c
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63368/2
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Sridhar Siricilla has uploaded a new patch set (#5) to the change originally created by Reka Norman. ( https://review.coreboot.org/c/coreboot/+/63365 )
Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
soc/intel/alderlake: Add support to update descriptor at runtime
On nereid, we need to update the descriptor based on fw_config (see
the following patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.
This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic.
BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.
Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/bootblock/update_descriptor.c
M src/soc/intel/alderlake/include/soc/bootblock.h
4 files changed, 94 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/5
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