coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts
by 9elements QA (Code Review) 05 Apr '22

05 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63282 ) Change subject: mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99602 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99601 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/99600 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/99599 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/99598 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99597 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/99596 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/99595 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/99594 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/99593 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/99592 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/99591 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99590 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/99589 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/99588 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/99587 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Gerrit-Change-Number: 63282 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 16:51:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Correct samsung part number value in S...
by Karthik Ramasubramanian (Code Review) 05 Apr '22

05 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63354 ) Change subject: mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD data ...................................................................... mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD data The value at offset 329 should be: 0x4B -> "K" not 0x48 -> "H" in ASCII code. BUG=b:224884904 TEST=Build, confirm the part number is matched the corresponding parts Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved Robert Zieba: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex b/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex index 00b26e6..3019147 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex @@ -18,7 +18,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 48 34 55 42 45 33 44 +00 00 00 00 00 00 00 00 00 4B 34 55 42 45 33 44 34 41 42 2D 4D 47 43 4C 00 00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Gerrit-Change-Number: 63354 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superiotool/ite: add IT8625E EC registers
by build bot (Jenkins) (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63310 ) Change subject: superiotool/ite: add IT8625E EC registers ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Gerrit-Change-Number: 63310 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Apr 2022 16:01:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns ...................................................................... Patch Set 26: Code-Review+1 (5 comments) File src/mainboard/teleplatforms/D4E4S16P8/Kconfig: https://review.coreboot.org/c/coreboot/+/57194/comment/e056a5cd_baba51e2 PS26, Line 10: select SUPPORT_CPU_UCODE_IN_CBFS : select FSP_CAR : select CPU_INTEL_COMMON : select PARALLEL_MP_AP_WORK : select SOC_INTEL_COMMON_BLOCK_FAST_SPI Shouldn't these be selected by DNV-NS Kconfig? File src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard_pci_irqs.asl: https://review.coreboot.org/c/coreboot/+/57194/comment/a4661940_e6af7519 PS21, Line 3: board specific > Well it's coupled with devicetree. […] Ack File src/mainboard/teleplatforms/D4E4S16P8/devicetree.cb: https://review.coreboot.org/c/coreboot/+/57194/comment/9e60f6e2_16e81840 PS26, Line 49: 06 This device number is suspicious, isn't this downstream of the root port? File src/mainboard/teleplatforms/D4E4S16P8/ramstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/90c52d16_057d9d4b PS21, Line 26: SMBUS_IO_BASE > This is ramstage, smbus_base() is romstage. […] Ack https://review.coreboot.org/c/coreboot/+/57194/comment/856b3d0b_a0cafd36 PS21, Line 28: (tmp < 0x20 || tmp > 0x7f) > Not sure if it looks like what you intended? Looks good, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 26 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Denverton-NS boards: Factor out common PCI IRQ config
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60102 ) Change subject: Denverton-NS boards: Factor out common PCI IRQ config ...................................................................... Abandoned Not correct -- To view, visit https://review.coreboot.org/c/coreboot/+/60102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f15f4781fbef7bee1f0cd40692180ec49acd9f Gerrit-Change-Number: 60102 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Kangheui Won, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Meera Ravindranath, Eric Lai, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/62856/comment/5104c122_6df4d1e2 PS2, Line 119: device pci 12.0 alias ish off end > But as long as Intel change here https://github. […] Looks like the documentation is wrong. I see the following on the public datasheet (691222-001): https://i.imgur.com/AiA2TL8.png It says UFS is PCI D18:F0, but that's the same as ISH. I'd rather trust code: https://github.com/slimbootloader/slimbootloader/blob/master/Silicon/Alderl… -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:27:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Jakub Czapiga (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/1ae2d367_edbcb5e5 PS3, Line 9: #3461454 > can you make this a link, e.g. […] Wait a minute. CONFIG_LP_VBOOT_LIB=y should be set by default. It defaults to 'y' for ChromeOS builds. And depthcharge should always be built with CONFIG_LP_CHROMEOS=y. I do not see a reason to enable it in libpayload defconfig. If one wants it, they should enable it on purpose, because it is not necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Sean Rhodes, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62994 ) Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
by Tim Wawrzynczak (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Felix Singer, Subrata Banik, Maulik V Vaghela, Christian Walter, Meera Ravindranath, Arthur Heymans, Lean Sheng Tan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63303 ) Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63303/comment/ffd2071b_eb7453fe PS3, Line 8: : The FSP needs to program VrPowerDeliverDesign configuration per : platform according to the platform capabilities to avoid incorrect : electrial/power parameters. This value is an enum of the available : power delivery segments that are defined in the Platform Design : Guide. if I am understanding correctly (and to be a little more specific), the FSP will read the SKU information to determine the VR configuration, unless you override this UPD -- To view, visit https://review.coreboot.org/c/coreboot/+/63303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74859e6735e59a15084a9e690b43f68341862833 Gerrit-Change-Number: 63303 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Sean Rhodes (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62994 ) Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... Patch Set 6: (1 comment) File src/ec/starlabs/merlin/variants/cezanne/emem.asl: https://review.coreboot.org/c/coreboot/+/62994/comment/52f238fc_bfebba11 PS4, Line 138: Offset(0xf7), : TBTC, 8, // Thunderbolt Command : TBTP, 8, // Thunderbolt Data Port : TBTD, 8, // Thunderbolt Data : TBTA, 8, // Thunderbolt Acknowledge : TBTG, 16, // Thunderbolt DBG Data > If possible (i.e. if it doesn't cause errors), I wouldn't define these fields. […] I don't think it will (2 boards still need a lot of work to say for sure) - so I think for now, go halfway and I'll scrap them later if nothing breaks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:20:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022