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Hello build bot (Jenkins), Martin Roth, Marshall Dawson, Julius Werner, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56122
to look at the new patch set (#10).
Change subject: Makefile.inc: Add x86 bootblock as a separate target
......................................................................
Makefile.inc: Add x86 bootblock as a separate target
Some platforms don't need a top aligned bootblock in cbfs like Intel
APL or modern AMD platforms as the bootblock is loaded differently.
So they don't need the top aligned cbfs bootblock.
To not clutter the main make file move out adding the bootblock.
Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/Kconfig
M src/arch/x86/Makefile.inc
M src/cpu/intel/fit/Makefile.inc
4 files changed, 25 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56122/10
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Change subject: ChromeOS: Promote variant_cros_gpio()
......................................................................
Patch Set 17:
(1 comment)
File src/vendorcode/google/chromeos/chromeos.h:
https://review.coreboot.org/c/coreboot/+/58897/comment/884dc9ab_bfac4072
PS17, Line 100: variant_cros_gpios
> Yes, but just it feels odd to have a common, visible-outside-mainboard-scope function prefixed with […]
Well there is CB:58899 already to play with.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63310 )
Change subject: superiotool/ite: add IT8625E EC registers
......................................................................
Patch Set 4: Verified+1
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/62856/comment/5104c122_6df4d1e2
PS2, Line 119: device pci 12.0 alias ish off end
> But as long as Intel change here https://github. […]
Looks like the documentation is wrong. I see the following on the public datasheet (691222-001): https://i.imgur.com/AiA2TL8.png
It says UFS is PCI D18:F0, but that's the same as ISH. I'd rather trust code: https://github.com/slimbootloader/slimbootloader/blob/master/Silicon/Alderl…
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Change subject: libpayload/defconfig: enable vboot Lib Build
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63240/comment/1ae2d367_edbcb5e5
PS3, Line 9: #3461454
> can you make this a link, e.g. […]
Wait a minute. CONFIG_LP_VBOOT_LIB=y should be set by default. It defaults to 'y' for ChromeOS builds. And depthcharge should always be built with CONFIG_LP_CHROMEOS=y. I do not see a reason to enable it in libpayload defconfig. If one wants it, they should enable it on purpose, because it is not necessary.
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards
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Patch Set 6: Code-Review+2
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