coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Tim Wawrzynczak (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Jes Klinke, Christian Walter, Julius Werner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/63158/comment/a760058e_b953c6a4 PS11, Line 32: MAINBOARD_HAS_I2C_TPM_TI50 > That is right, thanks. […] Brask is also cr50 only -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 12 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 18:08:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by build bot (Jenkins) (Code Review) 05 Apr '22

05 Apr '22

1 0

Change in coreboot[master]: amdfwtool: Add a macro to set explicitly second gen for old SOCs
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63319 ) Change subject: amdfwtool: Add a macro to set explicitly second gen for old SOCs ...................................................................... amdfwtool: Add a macro to set explicitly second gen for old SOCs It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 80595ddb..23273e6 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1383,6 +1383,8 @@ } switch (soc_id) { case PLATFORM_STONEYRIDGE: + amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; + amd_romsig->efs_gen.reserved = ~0; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; @@ -1390,6 +1392,8 @@ case PLATFORM_PICASSO: /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. * Leave as 0xffffffff for first gen */ + amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; + amd_romsig->efs_gen.reserved = ~0; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1410,6 +1414,7 @@ case PLATFORM_MENDOCINO: case PLATFORM_SABRINA: amd_romsig->efs_gen.gen = EFS_SECOND_GEN; + amd_romsig->efs_gen.reserved = 0; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1803,7 +1808,6 @@ amd_romsig->imc_entry = 0; amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; - amd_romsig->efs_gen.reserved = 0; if (soc_id != PLATFORM_UNKNOWN) { retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index a241316..3af4e94 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -88,6 +88,7 @@ } __attribute__((packed)); #define EFS_SECOND_GEN 0 +#define EFS_BEFORE_SECOND_GEN 1 typedef struct _embedded_firmware { uint32_t signature; /* 0x55aa55aa */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Gerrit-Change-Number: 63319 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [RFC] Replace some ENV_ROMSTAGE conditionals
by Kyösti Mälkki (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Christian Walter, Julius Werner, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63376 ) Change subject: [RFC] Replace some ENV_ROMSTAGE conditionals ...................................................................... [RFC] Replace some ENV_ROMSTAGE conditionals CBMEM_INIT_HOOKS that test for ENV_ROMSTAGE typically handle initial creation of the CBMEM entry with cbmem_add(). Add intermediate ENV_STAGE_CREATES_CBMEM such that executing said CBMEM_INIT_HOOK can be moved under ENV_BOOTBLOCK. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/rules.h M src/lib/cbfs.c M src/security/tpm/tspi/log.c M src/security/vboot/common.c M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/common/pi/heapmanager.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/quark/storage_test.c M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 14 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/63376/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index e6067da..6319520 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -101,7 +101,7 @@ uint32_t *cbmem_loc; const void *hob_list; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*cbmem_loc)); diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 09b3120..c3e1a4f 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -681,7 +681,7 @@ struct ehci_debug_info *dbg_info_cbmem; int rv; - if (ENV_ROMSTAGE) { + if (ENV_STAGE_CREATES_CBMEM) { /* Move state from CAR to CBMEM. */ struct ehci_debug_info *dbg_info = dbgp_ehci_info(); dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 2a9a982..0cd6db7 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -126,7 +126,7 @@ { struct vpd_cbmem *cbmem; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; timestamp_add_now(TS_COPYVPD_START); diff --git a/src/include/rules.h b/src/include/rules.h index 02b55c5..87aca60 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -292,6 +292,8 @@ #define ENV_INITIAL_STAGE ENV_BOOTBLOCK #endif +#define ENV_STAGE_CREATES_CBMEM ENV_ROMSTAGE + #if ENV_X86 #define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE #elif ENV_RISCV diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bc38693..512f5d2 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -28,7 +28,7 @@ static void switch_to_postram_cache(int unused) { - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; if (_preram_cbfs_cache != _postram_cbfs_cache) diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 1696231..5112fd4 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -127,7 +127,7 @@ struct tcpa_table *ram_log = NULL; int i; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; if (CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index d4c8184..41a7f70 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -72,7 +72,7 @@ vb2_error_t rv; const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c index 1251721..639e5b1 100644 --- a/src/soc/amd/common/block/pm/chipset_state.c +++ b/src/soc/amd/common/block/pm/chipset_state.c @@ -25,7 +25,7 @@ { struct chipset_power_state *state; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); diff --git a/src/soc/amd/common/pi/heapmanager.c b/src/soc/amd/common/pi/heapmanager.c index 6f69fca..f662535 100644 --- a/src/soc/amd/common/pi/heapmanager.c +++ b/src/soc/amd/common/pi/heapmanager.c @@ -12,7 +12,7 @@ static void EmptyHeap(int unused) { - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; void *BiosManagerPtr = agesa_heap_base(); diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index e283b46..a8e8a29 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -21,7 +21,7 @@ struct chipset_power_state *ps_cbmem; struct chipset_power_state *ps_car; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; ps_car = &power_state; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 688c830..e653db9 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -73,7 +73,7 @@ { struct chipset_power_state *ps_cbmem; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 0fc2218..b23dff2 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -231,7 +231,7 @@ struct sdhci_ctrlr *sdhci_ctrlr; size_t size = sizeof(drivers_storage); - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; /* Locate the data structures in CBMEM */ diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 4946b53..1534b29 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -134,7 +134,7 @@ struct mem_chip_info *mc; size_t size; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; if (!CONFIG(USE_CBMEM_DRAM_INFO)) { diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ec682da..66415f1 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -32,7 +32,7 @@ { void *mem_region_base = NULL; - if (!ENV_ROMSTAGE) + if (!ENV_STAGE_CREATES_CBMEM) return; /* Add cbmem table */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Gerrit-Change-Number: 63376 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by Kyösti Mälkki (Code Review) 05 Apr '22

05 Apr '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63375 ) Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... [RFC] CBMEM: Have INIT_HOOKS in every stage There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. Approach here adds no-op init hook calls for every stage, but may otherwise provide cleaner implementation. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_bert_storage.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/lib/cbfs.c M src/lib/cbmem_console.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/timestamp.c M src/security/tpm/tspi/log.c M src/security/vboot/common.c M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/common/pi/heapmanager.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/quark/storage_test.c M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 22 files changed, 104 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63375/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 8559c06..86dde50 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -579,6 +579,9 @@ static void bert_storage_setup(int unused) { + if (!ENV_RAMSTAGE) + return; + /* Always start with a blank bert region. Make sure nothing is * maintained across reboots or resumes. */ @@ -596,4 +599,4 @@ memset(bert_region_base, 0, bert_region_size); } -RAMSTAGE_CBMEM_INIT_HOOK(bert_storage_setup) +CBMEM_INIT_HOOK(bert_storage_setup) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 9144eaa..e6067da 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -100,6 +100,10 @@ { uint32_t *cbmem_loc; const void *hob_list; + + if (!ENV_ROMSTAGE) + return; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*cbmem_loc)); if (cbmem_loc == NULL) die("Error: Could not add cbmem area for hob list.\n"); @@ -109,7 +113,7 @@ *cbmem_loc = (uintptr_t)hob_list; } -ROMSTAGE_CBMEM_INIT_HOOK(save_hob_list); +CBMEM_INIT_HOOK(save_hob_list); const void *fsp_get_hob_list(void) { diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 2fbdf3a..09b3120 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -707,9 +707,7 @@ printk(BIOS_DEBUG, "usbdebug: " ENV_STRING " starting...\n"); } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); -POSTCAR_CBMEM_INIT_HOOK(migrate_ehci_debug); -RAMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); +CBMEM_INIT_HOOK(migrate_ehci_debug); int dbgp_ep_is_active(struct dbgp_pipe *pipe) { diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 32ec0a0..2a9a982 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -126,6 +126,9 @@ { struct vpd_cbmem *cbmem; + if (!ENV_ROMSTAGE) + return; + timestamp_add_now(TS_COPYVPD_START); init_vpd_rdevs(); @@ -295,4 +298,4 @@ return true; } -ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) +CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index cd7751c..dd4d506 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -106,49 +106,15 @@ void cbmem_list(void); void cbmem_add_records_to_cbtable(struct lb_header *header); -#if ENV_RAMSTAGE -#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_rom_ = init_fn_; -#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ +#define CBMEM_INIT_HOOK(init_fn_) \ static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks"))) = init_fn_; -#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_pc_ = init_fn_; -#elif ENV_ROMSTAGE -#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ - static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ - section(".rodata.cbmem_init_hooks"))) = init_fn_; -#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_ram_ = init_fn_; -#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_pc_ = init_fn_; -#elif ENV_POSTCAR -#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_rom_ = init_fn_; -#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_ram_ = init_fn_; -#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) \ - static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ - section(".rodata.cbmem_init_hooks"))) = init_fn_; -#else -#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_rom_ = init_fn_; -#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_ram_ = init_fn_; -#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_pc_ = init_fn_; -#endif /* ENV_RAMSTAGE */ /* Early hooks get executed before other hooks. Use sparingly for hooks that create CBMEM regions which need to remain in a constant location across boot modes. */ -#if ENV_ROMSTAGE -#define ROMSTAGE_CBMEM_INIT_HOOK_EARLY(init_fn_) \ +#define CBMEM_INIT_HOOK_EARLY(init_fn_) \ static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks_early"))) = init_fn_; -#else -#define ROMSTAGE_CBMEM_INIT_HOOK_EARLY(init_fn_) __attribute__((unused)) \ - static cbmem_init_hook_t init_fn_ ## _unused_rom_ = init_fn_; -#endif /* ENV_ROMSTAGE */ /* * Returns 0 for the stages where we know that cbmem does not come online. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c8ca14c..bc38693 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -28,11 +28,14 @@ static void switch_to_postram_cache(int unused) { + if (!ENV_ROMSTAGE) + return; + if (_preram_cbfs_cache != _postram_cbfs_cache) mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); } -ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); +CBMEM_INIT_HOOK(switch_to_postram_cache); enum cb_err _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mdata, struct region_device *rdev) @@ -672,7 +675,6 @@ return &ro; } -#if !CONFIG(NO_CBFS_MCACHE) static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) { if (!cbd) @@ -690,8 +692,13 @@ static void cbfs_mcache_migrate(int unused) { + if (CONFIG(NO_CBFS_MCACHE)) + return; + + if (!ENV_ROMSTAGE) + return; + mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE); mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE); } -ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate) -#endif +CBMEM_INIT_HOOK(cbfs_mcache_migrate) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 783f336..ebdab7f 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -170,9 +170,7 @@ /* Run the romstage hook early so that the console region is one of the earliest created, and therefore more likely to stay in the same place even across different boot modes where some other regions may sometimes not get created (e.g. RW_MCACHE in vboot recovery mode). */ -ROMSTAGE_CBMEM_INIT_HOOK_EARLY(cbmemc_reinit) -RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) -POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) +CBMEM_INIT_HOOK_EARLY(cbmemc_reinit) #if CONFIG(CONSOLE_CBMEM_DUMP_TO_UART) void cbmem_dump_console_to_uart(void) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index d498597..dd206f1 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -158,6 +158,4 @@ stage_cache_create_empty(); } -ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) -RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) -POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) +CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 2511255..f0e1880 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -273,24 +273,8 @@ return rdev_writeat(&rdev, buffer, 0, size); } -static void fmap_register_cbmem_cache(int unused) -{ - const struct cbmem_entry *e; - /* Find the FMAP cache installed by previous stage */ - e = cbmem_entry_find(CBMEM_ID_FMAP); - /* Don't set fmap_cache so that find_fmap_directory will use regular path */ - if (!e) - return; - - rdev_chain_mem(&fmap_cache, cbmem_entry_start(e), cbmem_entry_size(e)); -} - -/* - * The main reason to copy the FMAP into CBMEM is to make it available to the - * OS on every architecture. As side effect use the CBMEM copy as cache. - */ -static void fmap_setup_cbmem_cache(int unused) +static void fmap_add_cbmem_cache(void) { struct region_device fmrd; @@ -311,11 +295,32 @@ cbmem_entry_remove(cbmem_entry_find(CBMEM_ID_FMAP)); return; } - - /* Finally advertise the cache for the current stage */ - fmap_register_cbmem_cache(unused); } -ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) -RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) -POSTCAR_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) +static void fmap_register_cbmem_cache(void) +{ + const struct cbmem_entry *e; + + /* Find the FMAP cache installed by previous stage */ + e = cbmem_entry_find(CBMEM_ID_FMAP); + /* Don't set fmap_cache so that find_fmap_directory will use regular path */ + if (!e) + return; + + rdev_chain_mem(&fmap_cache, cbmem_entry_start(e), cbmem_entry_size(e)); +} + +/* + * The main reason to copy the FMAP into CBMEM is to make it available to the + * OS on every architecture. As side effect use the CBMEM copy as cache. + */ +static void fmap_setup_cbmem_cache(int unused) +{ + if (ENV_ROMSTAGE) + fmap_add_cbmem_cache(); + + /* Finally advertise the cache for the current stage */ + fmap_register_cbmem_cache(); +} + +CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b92975f..ac36cd3 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -279,9 +279,7 @@ return (timestamp_get() - ts->base_time) / ts->tick_freq_mhz; } -ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) -POSTCAR_CBMEM_INIT_HOOK(timestamp_reinit) -RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +CBMEM_INIT_HOOK(timestamp_reinit) /* Provide default timestamp implementation using monotonic timer. */ uint64_t __weak timestamp_get(void) diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 1d6f9ac..1696231 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -121,13 +121,18 @@ tclt->num_entries = 0; } -#if !CONFIG(VBOOT_RETURN_FROM_VERSTAGE) static void recover_tcpa_log(int is_recovery) { struct tcpa_table *preram_log = (struct tcpa_table *)_tpm_tcpa_log; struct tcpa_table *ram_log = NULL; int i; + if (!ENV_ROMSTAGE) + return; + + if (CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) + return; + if (preram_log->num_entries > MAX_PRERAM_TCPA_LOG_ENTRIES) { printk(BIOS_WARNING, "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); return; @@ -154,7 +159,6 @@ memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); } } -ROMSTAGE_CBMEM_INIT_HOOK(recover_tcpa_log); -#endif +CBMEM_INIT_HOOK(recover_tcpa_log); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, tcpa_log_dump, NULL); diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index f3e2e4b..d4c8184 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -71,8 +71,13 @@ { vb2_error_t rv; const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; + + if (!ENV_ROMSTAGE) + return; + void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wb_cbmem != NULL); + /* * On platforms where VBOOT_STARTS_BEFORE_BOOTBLOCK, the verification * occurs before the main processor starts running. The vboot data- @@ -96,4 +101,4 @@ assert(rv == VB2_SUCCESS); } -ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) +CBMEM_INIT_HOOK(vboot_setup_cbmem) diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c index 42d1a15..1251721 100644 --- a/src/soc/amd/common/block/pm/chipset_state.c +++ b/src/soc/amd/common/block/pm/chipset_state.c @@ -25,10 +25,12 @@ { struct chipset_power_state *state; - state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + if (!ENV_ROMSTAGE) + return; + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); if (state) memcpy(state, &chipset_state, sizeof(*state)); } -ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem); +CBMEM_INIT_HOOK(add_chipset_state_cbmem); diff --git a/src/soc/amd/common/pi/heapmanager.c b/src/soc/amd/common/pi/heapmanager.c index 699bb53..6f69fca 100644 --- a/src/soc/amd/common/pi/heapmanager.c +++ b/src/soc/amd/common/pi/heapmanager.c @@ -12,10 +12,15 @@ static void EmptyHeap(int unused) { + if (!ENV_ROMSTAGE) + return; + void *BiosManagerPtr = agesa_heap_base(); memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } +CBMEM_INIT_HOOK(EmptyHeap) + /* * Name agesa_GetTempHeapBase * Brief description Get the location for TempRam, the target location in @@ -127,8 +132,6 @@ memset(SecondNodePtr, 0, sizeof(BIOS_BUFFER_NODE)); } -ROMSTAGE_CBMEM_INIT_HOOK(EmptyHeap) - AGESA_STATUS agesa_AllocateBuffer(uint32_t Func, uintptr_t Data, void *ConfigPtr) { diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 8ac2eb5..59d23e0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -215,4 +215,4 @@ acpi_pm_gpe_add_events_print_events(); } } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) +CBMEM_INIT_HOOK(migrate_power_state) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 74238e2..c857524 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -32,7 +32,7 @@ } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) +CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index daa1b2d..35fdd72 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -26,7 +26,7 @@ } memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +CBMEM_INIT_HOOK(migrate_power_state); struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index 12bee7d..e283b46 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -21,6 +21,9 @@ struct chipset_power_state *ps_cbmem; struct chipset_power_state *ps_car; + if (!ENV_ROMSTAGE) + return; + ps_car = &power_state; ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); @@ -30,7 +33,7 @@ } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) +CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(const struct chipset_power_state *ps) diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index a2e3e9e..688c830 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -73,15 +73,17 @@ { struct chipset_power_state *ps_cbmem; - ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + if (!ENV_ROMSTAGE) + return; + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } -ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) +CBMEM_INIT_HOOK(migrate_power_state) static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 04c6736..0fc2218 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -225,13 +225,15 @@ } #endif -#if ENV_ROMSTAGE static void copy_storage_structures(int is_recovery) { struct storage_media *media; struct sdhci_ctrlr *sdhci_ctrlr; size_t size = sizeof(drivers_storage); + if (!ENV_ROMSTAGE) + return; + /* Locate the data structures in CBMEM */ media = cbmem_add(CBMEM_ID_STORAGE_DATA, size); ASSERT(media != NULL); @@ -242,5 +244,4 @@ media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr; } -ROMSTAGE_CBMEM_INIT_HOOK(copy_storage_structures); -#endif +CBMEM_INIT_HOOK(copy_storage_structures); diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index ab1ccb5..4946b53 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -134,6 +134,9 @@ struct mem_chip_info *mc; size_t size; + if (!ENV_ROMSTAGE) + return; + if (!CONFIG(USE_CBMEM_DRAM_INFO)) { printk(BIOS_DEBUG, "DRAM-K: CBMEM DRAM info is unsupported (USE_CBMEM_DRAM_INFO)\n"); @@ -146,7 +149,7 @@ fill_dram_info(mc, curr_ddr_info); } -ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); +CBMEM_INIT_HOOK(add_mem_chip_info); static int run_dram_blob(struct dramc_param *dparam) { diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 43b6399..ec682da 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -19,7 +19,7 @@ #define QCLIB_VERSION 0 -/* store QcLib return data until ROMSTAGE_CBMEM_INIT_HOOK runs */ +/* store QcLib return data until CBMEM_INIT_HOOK runs */ static void *mem_chip_addr; static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) @@ -32,6 +32,9 @@ { void *mem_region_base = NULL; + if (!ENV_ROMSTAGE) + return; + /* Add cbmem table */ if (sizeof(struct mem_chip_info) != 0) mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, @@ -42,7 +45,7 @@ memcpy(mem_region_base, mem_chip_addr, sizeof(struct mem_chip_info)); } -ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); +CBMEM_INIT_HOOK(add_mem_chip_info); struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/63169/comment/08a6f192_a38d440e PS5, Line 955: static const char * const cse_regions[] = {"RO", "RW"}; > Since you are also reusing this ("RO" anyway) on line 793, does it make sense to move this declarati […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 17:34:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Kane Chen. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63169 to look at the new patch set (#6). Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Also, did boot test on Kano system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 33 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63169/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns
by Kyösti Mälkki (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Dmitry Ponamorev, Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns ...................................................................... Patch Set 26: (1 comment) File src/mainboard/teleplatforms/D4E4S16P8/devicetree.cb: https://review.coreboot.org/c/coreboot/+/57194/comment/eca86bf6_7e6dcc39 PS26, Line 49: 06 > This device number is suspicious, isn't this downstream of the root port? Right, they are wrong, it's listing the bus number as device number. Should be fine to just remove these, I'll test it. -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 26 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 17:33:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
by Jon Murphy (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Paul Menzel, Chris Wang, Karthik Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63295 ) Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Gerrit-Change-Number: 63295 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 17:22:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics
by build bot (Jenkins) (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56118 ) Change subject: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics ...................................................................... Patch Set 12: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Gerrit-Change-Number: 56118 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 17:18:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022