Change in coreboot[master]: amdfwtool: Add a macro to set explicitly second gen for old SOCs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63319 )

Change subject: amdfwtool: Add a macro to set explicitly second gen for old SOCs
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amdfwtool: Add a macro to set explicitly second gen for old SOCs

It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 6 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 80595ddb..23273e6 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1383,6 +1383,8 @@
    }
    switch (soc_id) {
    case PLATFORM_STONEYRIDGE:
+		amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
+		amd_romsig->efs_gen.reserved = ~0;
    	amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
    	amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
    	break;
@@ -1390,6 +1392,8 @@
    case PLATFORM_PICASSO:
    	/* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
    	 * Leave as 0xffffffff for first gen */
+		amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
+		amd_romsig->efs_gen.reserved = ~0;
    	amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
    	amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
    	switch (efs_spi_micron_flag) {
@@ -1410,6 +1414,7 @@
    case PLATFORM_MENDOCINO:
    case PLATFORM_SABRINA:
    	amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
+		amd_romsig->efs_gen.reserved = 0;
    	amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
    	amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
    	switch (efs_spi_micron_flag) {
@@ -1803,7 +1808,6 @@
    amd_romsig->imc_entry = 0;
    amd_romsig->gec_entry = 0;
    amd_romsig->xhci_entry = 0;
-	amd_romsig->efs_gen.reserved = 0;

if (soc_id != PLATFORM_UNKNOWN) {
    	retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode,
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index a241316..3af4e94 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -88,6 +88,7 @@
 } __attribute__((packed));

#define EFS_SECOND_GEN 0
+#define EFS_BEFORE_SECOND_GEN 1

typedef struct _embedded_firmware {
    uint32_t signature; /* 0x55aa55aa */