coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Jeff Daly, Subrata Banik, Mariusz Szafrański, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63367 ) Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/include/soc/msr.h: https://review.coreboot.org/c/coreboot/+/63367/comment/e46f2f64_03f78368 PS1, Line 10: MSR_VR_MISC_CONFIG2 > > Yeah I see it defined in the EDS, but FSP does not program it, and neither does coreboot. […] Hmmm, I guess this MSR only exists on platforms with FIVR? If so, I'd expect TGL to have this MSR as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/63367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b203aa243ab97e3569f7347b424dd72318bd65f Gerrit-Change-Number: 63367 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Tim Wawrzynczak (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jakub Czapiga, Selma Bensaid. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/c7c6799f_b4b118fb PS3, Line 9: #3461454 can you make this a link, e.g. `https://crrev.com/c/3461454` -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Promote variant_cros_gpio()
by Tim Wawrzynczak (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro, Angel Pons, Kyösti Mälkki, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58897 ) Change subject: ChromeOS: Promote variant_cros_gpio() ...................................................................... Patch Set 17: (1 comment) File src/vendorcode/google/chromeos/chromeos.h: https://review.coreboot.org/c/coreboot/+/58897/comment/fcfd7c97_de658c57 PS17, Line 100: variant_cros_gpios > It's currently defined at variant-scope in most cases Yes, but just it feels odd to have a common, visible-outside-mainboard-scope function prefixed with `variant_` :shrug -- To view, visit https://review.coreboot.org/c/coreboot/+/58897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Gerrit-Change-Number: 58897 Gerrit-PatchSet: 17 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:12:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Promote variant_cros_gpio()
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro, Kyösti Mälkki, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58897 ) Change subject: ChromeOS: Promote variant_cros_gpio() ...................................................................... Patch Set 17: (1 comment) File src/vendorcode/google/chromeos/chromeos.h: https://review.coreboot.org/c/coreboot/+/58897/comment/45e09451_0577f3f2 PS17, Line 100: variant_cros_gpios > suggestion: now in maybe another patch, a better name might be […] It's currently defined at variant-scope in most cases -- To view, visit https://review.coreboot.org/c/coreboot/+/58897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Gerrit-Change-Number: 58897 Gerrit-PatchSet: 17 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:05:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
by Angel Pons (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Felix Singer, Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Christian Walter, Meera Ravindranath, Arthur Heymans, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63303 ) Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74859e6735e59a15084a9e690b43f68341862833 Gerrit-Change-Number: 63303 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 15:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63282 ) Change subject: mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts ...................................................................... mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This commit overrides the default SPD files used for these parts BUG=b:224884904 TEST=Verified that Dewatt SKU1 and SKU3 boot with changes Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 9c4a7e4..c6b64cf 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -13,6 +13,6 @@ SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 6(0b0110) SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 7(0b0111) SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 8(0b1000) -SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4U6E3S4AB-MGCL.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL +SPD_SOURCES += src/mainboard/google/guybrush/variants/dewatt/memory/K4U6E3S4AB-MGCL.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 10(0b1010) -SPD_SOURCES += $(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/memory/K4UBE3D4AB-MGCL.hex # ID = 11(0b1011) Parts = K4UBE3D4AB-MGCL +SPD_SOURCES += src/mainboard/google/guybrush/variants/dewatt/memory/K4UBE3D4AB-MGCL.hex # ID = 11(0b1011) Parts = K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt index 9d79210..f2c3024 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt @@ -7,8 +7,8 @@ K4U6E3S4AA-MGCR H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR -K4U6E3S4AB-MGCL,*9 +K4U6E3S4AB-MGCL,9,K4U6E3S4AB-MGCL.hex H54G46CYRBX267 MT53E512M32D1NP-046 WT:B H54G56CYRBX247 -K4UBE3D4AB-MGCL,*11 +K4UBE3D4AB-MGCL,11,K4UBE3D4AB-MGCL.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/63282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Gerrit-Change-Number: 63282 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Add ability to override SPD file for parts
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63281 ) Change subject: util/spd_tools: Add ability to override SPD file for parts ...................................................................... util/spd_tools: Add ability to override SPD file for parts This commit adds the ability to override the SPD file that is used for a specific part. BUG=b:224884904 TEST=Verified that generated makefile uses specified SPD file and that it remains unchanged when this capability is not used Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M util/spd_tools/README.md M util/spd_tools/src/part_id_gen/part_id_gen.go 2 files changed, 64 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md index 01bc417..6f09f56 100644 --- a/util/spd_tools/README.md +++ b/util/spd_tools/README.md @@ -459,14 +459,16 @@ * The memory technology used by the board, e.g. lp4x. * The path to the directory where the generated Makefile.inc should be placed. * A CSV file containing a list of the memory parts used by the board, with an -* optional fixed or exclusive ID for each part. A fixed ID is simply an integer -* and it ensure that part (and any that share the same SPD) will be assigned -* that ID. An exclusive ID is prefixed with `*` and ensures that only parts with -* the same exclusive ID will be assigned that ID, even if they would otherwise -* share the same ID. +* optional fixed or exclusive ID for each part and an optional SPD override file. +* A fixed ID is simply an integer and it ensure that part (and any that share the same SPD) +* will be assigned that ID. An exclusive ID is prefixed with `*` and ensures that +* only parts with the same exclusive ID will be assigned that ID, even if they would +* otherwise share the same ID. When using an SPD override file, the file will be searched +* for in the directory where mem_parts_used is located, if it is not found there then it +* will be searched for in the appropriate default spd directory. * NOTE: Only assign a fixed/exclusive ID if required for legacy reasons. -Example of a CSV file using fixed and exclusive IDs: +Example of a CSV file using fixed and exclusive IDs, and SPD file overrides: ``` K4AAG165WA-BCWE,1 @@ -475,6 +477,8 @@ K4A8G165WC-BCWE H5AN8G6NDJR-XNC,8 H5ANAG6NCMR-XNC,*9 +H9HCNNNCPMMLXR-NEE,,H9HCNNNCPMMLXR-NEE.hex +H54G56CYRBX247,4,H54G56CYRBX247.hex ``` Explanation: This will ensure that the SPDs for K4AAG165WA-BCWE and diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index 65e07f4..edbad9c 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -102,9 +102,10 @@ ) type usedPart struct { - partName string - index int - mapping mappingType + partName string + index int + mapping mappingType + SPDOverride string } func readPlatformsManifest(memTech string) (map[string]string, error) { @@ -183,30 +184,44 @@ } if len(fields) == 1 { - parts = append(parts, usedPart{fields[0], -1, Auto}) - } else if len(fields) == 2 { + parts = append(parts, usedPart{fields[0], -1, Auto, ""}) + } else { var mapping = Auto var assignedId = -1 var err error = nil + var spdOverride string = "" - if len(fields[1]) >= 2 && fields[1][0] == '*' { - // Exclusive mapping - mapping = Exclusive - assignedId, err = strconv.Atoi(fields[1][1:]) - } else { - mapping = Fixed - assignedId, err = strconv.Atoi(fields[1]) + // Second column, ID override + if len(fields) >= 2 { + if len(fields[1]) >= 2 && fields[1][0] == '*' { + // Exclusive mapping + mapping = Exclusive + assignedId, err = strconv.Atoi(fields[1][1:]) + } else if fields[1] != "" { + // Fixed mapping + mapping = Fixed + assignedId, err = strconv.Atoi(fields[1]) + } + } + + // Third column, SPD file override + if len(fields) >= 3 { + if len(fields[2]) == 0 { + err = fmt.Errorf("mem_parts_used_file file is incorrectly formatted, SPD file column is empty") + } else { + spdOverride = fields[2] + } } if err != nil { return nil, err } - if assignedId > MaxMemoryId || assignedId < 0 { + + if assignedId > MaxMemoryId { return nil, fmt.Errorf("Out of bounds assigned id %d for part %s", assignedId, fields[0]) } - parts = append(parts, usedPart{fields[0], assignedId, mapping}) - } else { - return nil, fmt.Errorf("mem_parts_used_file file is incorrectly formatted") + + parts = append(parts, usedPart{fields[0], assignedId, mapping, spdOverride}) } } @@ -288,7 +303,6 @@ // Assign parts with fixed ids first for _, p := range parts { - if p.index == -1 { continue } @@ -299,7 +313,7 @@ SPDFileName, ok := partToSPDMap[p.partName] if !ok { - return nil, fmt.Errorf("Failed to find part ", p.partName, " in SPD Manifest. Please add the part to global part list and regenerate SPD Manifest") + return nil, fmt.Errorf("Failed to find part %s in SPD Manifest. Please add the part to global part list and regenerate SPD Manifest", p.partName) } // Extend partIdList and assignedMapping with empty entries if needed @@ -396,7 +410,7 @@ * This function generates Makefile.inc under the variant directory path and adds assigned SPDs * to SPD_SOURCES. */ -func genMakefile(partIdList []partIds, makefileDirName string, SPDDir string) error { +func genMakefile(partIdList []partIds, makefileDirName string, SPDDir string, partsDir string) error { s := getFileHeader() s += fmt.Sprintf("SPD_SOURCES =\n") @@ -405,7 +419,18 @@ s += fmt.Sprintf("SPD_SOURCES += %v ", filepath.Join(SPDDir, SPDEmptyFileName)) s += fmt.Sprintf(" # ID = %d(0b%04b)\n", i, int64(i)) } else { - s += fmt.Sprintf("SPD_SOURCES += %v ", filepath.Join(SPDDir, partIdList[i].SPDFileName)) + SPDFileName := partIdList[i].SPDFileName + path := filepath.Join(partsDir, SPDFileName) + + // Check if the file exists in the directory of the parts file + if _, err := os.Stat(path); err != nil { + // File doesn't exist, check spd directory + path = filepath.Join(SPDDir, SPDFileName) + if _, err = os.Stat(path); err != nil { + return fmt.Errorf("Failed to write Makefile, SPD file '%s' doesn't exist", SPDFileName) + } + } + s += fmt.Sprintf("SPD_SOURCES += %v ", path) s += fmt.Sprintf(" # ID = %d(0b%04b) ", i, int64(i)) s += fmt.Sprintf(" Parts = %04s\n", partIdList[i].memParts) } @@ -442,12 +467,20 @@ log.Fatal(err) } + // Update our SPD maps with part specific overrides + for _, p := range parts { + if p.SPDOverride != "" { + partToSPDMap[p.partName] = p.SPDOverride + SPDToIndexMap[p.SPDOverride] = -1 + } + } + partIdList, err := genPartIdInfo(parts, partToSPDMap, SPDToIndexMap, makefileDir) if err != nil { log.Fatal(err) } - if err := genMakefile(partIdList, makefileDir, SPDDir); err != nil { + if err := genMakefile(partIdList, makefileDir, SPDDir, filepath.Dir(memPartsUsedFile)); err != nil { log.Fatal(err) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Gerrit-Change-Number: 63281 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Add ability to override SPD file for parts
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Attention is currently required from: Robert Zieba, Reka Norman, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63281 ) Change subject: util/spd_tools: Add ability to override SPD file for parts ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: can CB:62905 be reverted with this in place? -- To view, visit https://review.coreboot.org/c/coreboot/+/63281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Gerrit-Change-Number: 63281 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 14:50:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Battery Participant
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63316 ) Change subject: soc/intel/alderlake: Add HID for DPTF Battery Participant ...................................................................... soc/intel/alderlake: Add HID for DPTF Battery Participant HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/dptf.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index 59243ba..7016d8c 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -14,6 +14,8 @@ .tpch_device_hid = "INTC1049", /* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */ .tpwr_device_hid = "INTC1060", + /* _HID for the toplevel BAT1 device, typically \_SB.DPTF.BAT1 */ + .tbat_device_hid = "INTC1061", .tpch_method_names = { .set_fivr_low_clock_method = "RFC0", -- To view, visit https://review.coreboot.org/c/coreboot/+/63316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Gerrit-Change-Number: 63316 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add support for Battery participant
by Felix Held (Code Review) 05 Apr '22

05 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63315 ) Change subject: drivers/intel/dptf: Add support for Battery participant ...................................................................... drivers/intel/dptf: Add support for Battery participant As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add support for TBAT device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TBAT device Device (TBAT) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "TBAT") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/include/acpi/acpigen_dptf.h 5 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 4a5bd09..a4b3b09 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -76,6 +76,8 @@ return "TPCH"; case DPTF_POWER: return "TPWR"; + case DPTF_BATTERY: + return "TBAT"; default: return ""; } diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index a7a5760..c0e62b7 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -19,3 +19,10 @@ help When enabled, chip driver/intel/dptf will publish information to the SSDT for TPWR device. + +config DRIVERS_INTEL_DPTF_SUPPORTS_TBAT + def_bool n + depends on DRIVERS_INTEL_DPTF + help + When enabled, chip driver/intel/dptf will publish information to the + SSDT for TBAT device. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index ecb338b..27c7133 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -14,12 +14,14 @@ DPTF_GENERIC_PARTICIPANT_TYPE_TSR = 0x3, DPTF_GENERIC_PARTICIPANT_TYPE_TPCH = 0x5, DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER = 0xB, + DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY = 0xC, DPTF_GENERIC_PARTICIPANT_TYPE_POWER = 0x11, }; #define DEFAULT_CHARGER_STR "Battery Charger" #define DEFAULT_TPCH_STR "Intel PCH FIVR Participant" #define DEFAULT_POWER_STR "Power Participant" +#define DEFAULT_BATTERY_STR "Battery Participant" #define PMC_IPC_COMMAND_FIVR_SIZE 0x8 @@ -388,6 +390,26 @@ write_create_tpwr(platform_info); } +static void write_create_tbat(const struct dptf_platform_info *platform_info) +{ + acpigen_write_device("TBAT"); + acpigen_write_name("_HID"); + if (platform_info->tbat_device_hid != NULL) + dptf_write_hid(platform_info->use_eisa_hids, platform_info->tbat_device_hid); + acpigen_write_name_string("_UID", "TBAT"); + acpigen_write_name_string("_STR", DEFAULT_BATTERY_STR); + acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_device_end(); /* TBAT Battery Participant Device */ +} + + +static void write_tbat_methods(const struct dptf_platform_info *platform_info) +{ + write_create_tbat(platform_info); +} + + /* \_SB.DPTF - note: leaves the Scope open for child devices */ static void write_open_dptf_device(const struct device *dev, const struct dptf_platform_info *platform_info) @@ -429,6 +451,9 @@ if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPWR)) write_tpwr_methods(platform_info); + if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TBAT)) + write_tbat_methods(platform_info); + acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */ acpigen_pop_len(); /* Scope */ } diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h index c80e64a..ed25880 100644 --- a/src/drivers/intel/dptf/dptf.h +++ b/src/drivers/intel/dptf/dptf.h @@ -16,6 +16,7 @@ const char *fan_hid; const char *tpch_device_hid; const char *tpwr_device_hid; + const char *tbat_device_hid; struct { const char *set_fivr_low_clock_method; const char *set_fivr_high_clock_method; diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 0d49452..893256e 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -27,6 +27,7 @@ DPTF_TEMP_SENSOR_4, DPTF_TPCH, DPTF_POWER, + DPTF_BATTERY, DPTF_PARTICIPANT_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Gerrit-Change-Number: 63315 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-MessageType: merged

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