coreboot-gerrit March 2022

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Change in coreboot[master]: util/cbmem: Add FlameGraph-compatible timestamps output
by Jakub Czapiga (Code Review) 01 Mar '22

01 Mar '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62474 ) Change subject: util/cbmem: Add FlameGraph-compatible timestamps output ...................................................................... util/cbmem: Add FlameGraph-compatible timestamps output Flame graphs are used to visualize hierarchical data, like call stacks. Timestamps collected by coreboot can be processed to resemble profiler-like output, and thus can be feed to flame graph generation tools. TEST=Run on coreboot-enabled device and extract timestamps using -t/-T/-S options Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 --- M src/commonlib/include/commonlib/timestamp_serialized.h M util/cbmem/cbmem.c 2 files changed, 367 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62474/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 2f592c4..7033c4d 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -282,7 +282,7 @@ { TS_ME_END_OF_POST_END, "after sending EOP to ME"}, { TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"}, { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, - { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"}, + { TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"}, { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, { TS_CSE_FW_SYNC_START, "starting CSE firmware sync"}, { TS_CSE_FW_SYNC_END, "finished CSE firmware sync"}, @@ -313,4 +313,202 @@ { TS_POSTCAR_END, "end of postcar" }, }; +static const struct timestamp_id_to_enum_name { + uint32_t id; + const char *name; +} timestamp_enum_ids[] = { + { 0, "TS_START"}, + { TS_ROMSTAGE_START, "TS_ROMSTAGE_START" }, + { TS_INITRAM_START, "TS_INITRAM_START" }, + { TS_INITRAM_END, "TS_INITRAM_END" }, + { TS_ROMSTAGE_END, "TS_ROMSTAGE_END" }, + { TS_VBOOT_START, "TS_VBOOT_START" }, + { TS_VBOOT_END, "TS_VBOOT_END" }, + { TS_COPYRAM_START, "TS_COPYRAM_START" }, + { TS_COPYRAM_END, "TS_COPYRAM_END" }, + { TS_RAMSTAGE_START, "TS_RAMSTAGE_START" }, + { TS_BOOTBLOCK_START, "TS_BOOTBLOCK_START" }, + { TS_BOOTBLOCK_END, "TS_BOOTBLOCK_END" }, + { TS_COPYROM_START, "TS_COPYROM_START" }, + { TS_COPYROM_END, "TS_COPYROM_END" }, + { TS_ULZMA_START, "TS_ULZMA_START" }, + { TS_ULZMA_END, "TS_ULZMA_END" }, + { TS_ULZ4F_START, "TS_ULZ4F_START" }, + { TS_ULZ4F_END, "TS_ULZ4F_END" }, + { TS_DEVICE_ENUMERATE, "TS_DEVICE_ENUMERATE" }, + { TS_DEVICE_CONFIGURE, "TS_DEVICE_CONFIGURE" }, + { TS_DEVICE_ENABLE, "TS_DEVICE_ENABLE" }, + { TS_DEVICE_INITIALIZE, "TS_DEVICE_INITIALIZE" }, + { TS_OPROM_INITIALIZE, "TS_OPROM_INITIALIZE" }, + { TS_OPROM_COPY_END, "TS_OPROM_COPY_END" }, + { TS_OPROM_END, "TS_OPROM_END" }, + { TS_DEVICE_DONE, "TS_DEVICE_DONE" }, + { TS_CBMEM_POST, "TS_CBMEM_POST" }, + { TS_WRITE_TABLES, "TS_WRITE_TABLES" }, + { TS_FINALIZE_CHIPS, "TS_FINALIZE_CHIPS" }, + { TS_LOAD_PAYLOAD, "TS_LOAD_PAYLOAD" }, + { TS_ACPI_WAKE_JUMP, "TS_ACPI_WAKE_JUMP" }, + { TS_SELFBOOT_JUMP, "TS_SELFBOOT_JUMP" }, + { TS_POSTCAR_START, "TS_POSTCAR_START" }, + { TS_POSTCAR_END, "TS_POSTCAR_END" }, + { TS_DELAY_START, "TS_DELAY_START" }, + { TS_DELAY_END, "TS_DELAY_END" }, + { TS_READ_UCODE_START, "TS_READ_UCODE_START" }, + { TS_READ_UCODE_END, "TS_READ_UCODE_END" }, + { TS_ELOG_INIT_START, "TS_ELOG_INIT_START" }, + { TS_ELOG_INIT_END, "TS_ELOG_INIT_END" }, + { TS_COPYVER_START, "TS_COPYVER_START" }, + { TS_COPYVER_END, "TS_COPYVER_END" }, + { TS_TPMINIT_START, "TS_TPMINIT_START" }, + { TS_TPMINIT_END, "TS_TPMINIT_END" }, + { TS_VERIFY_SLOT_START, "TS_VERIFY_SLOT_START" }, + { TS_VERIFY_SLOT_END, "TS_VERIFY_SLOT_END" }, + { TS_HASH_BODY_START, "TS_HASH_BODY_START" }, + { TS_LOADING_END, "TS_LOADING_END" }, + { TS_HASHING_END, "TS_HASHING_END" }, + { TS_HASH_BODY_END, "TS_HASH_BODY_END" }, + { TS_TPMPCR_START, "TS_TPMPCR_START" }, + { TS_TPMPCR_END, "TS_TPMPCR_END" }, + { TS_TPMLOCK_START, "TS_TPMLOCK_START" }, + { TS_TPMLOCK_END, "TS_TPMLOCK_END" }, + { TS_EC_SYNC_START, "TS_EC_SYNC_START" }, + { TS_EC_HASH_READY, "TS_EC_HASH_READY" }, + { TS_EC_POWER_LIMIT_WAIT, "TS_EC_POWER_LIMIT_WAIT" }, + { TS_EC_SYNC_END, "TS_EC_SYNC_END" }, + { TS_COPYVPD_START, "TS_COPYVPD_START" }, + { TS_COPYVPD_RO_END, "TS_COPYVPD_RO_END" }, + { TS_COPYVPD_RW_END, "TS_COPYVPD_RW_END" }, + { TS_TPM_ENABLE_UPDATE_START, "TS_TPM_ENABLE_UPDATE_START" }, + { TS_TPM_ENABLE_UPDATE_END, "TS_TPM_ENABLE_UPDATE_END" }, + { TS_AGESA_INIT_RESET_START, "TS_AGESA_INIT_RESET_START" }, + { TS_AGESA_INIT_RESET_END, "TS_AGESA_INIT_RESET_END" }, + { TS_AGESA_INIT_EARLY_START, "TS_AGESA_INIT_EARLY_START" }, + { TS_AGESA_INIT_EARLY_END, "TS_AGESA_INIT_EARLY_END" }, + { TS_AGESA_INIT_POST_START, "TS_AGESA_INIT_POST_START" }, + { TS_AGESA_INIT_POST_END, "TS_AGESA_INIT_POST_END" }, + { TS_AGESA_INIT_ENV_START, "TS_AGESA_INIT_ENV_START" }, + { TS_AGESA_INIT_ENV_END, "TS_AGESA_INIT_ENV_END" }, + { TS_AGESA_INIT_MID_START, "TS_AGESA_INIT_MID_START" }, + { TS_AGESA_INIT_MID_END, "TS_AGESA_INIT_MID_END" }, + { TS_AGESA_INIT_LATE_START, "TS_AGESA_INIT_LATE_START" }, + { TS_AGESA_INIT_LATE_END, "TS_AGESA_INIT_LATE_END" }, + { TS_AGESA_INIT_RTB_START, "TS_AGESA_INIT_RTB_START" }, + { TS_AGESA_INIT_RTB_END, "TS_AGESA_INIT_RTB_END" }, + { TS_AGESA_INIT_RESUME_START, "TS_AGESA_INIT_RESUME_START" }, + { TS_AGESA_INIT_RESUME_END, "TS_AGESA_INIT_RESUME_END" }, + { TS_AGESA_S3_LATE_START, "TS_AGESA_S3_LATE_START" }, + { TS_AGESA_S3_LATE_END, "TS_AGESA_S3_LATE_END" }, + { TS_AGESA_S3_FINAL_START, "TS_AGESA_S3_FINAL_START" }, + { TS_AGESA_S3_FINAL_END, "TS_AGESA_S3_FINAL_END" }, + { TS_AMD_APOB_READ_START, "TS_AMD_APOB_READ_START" }, + { TS_AMD_APOB_ERASE_START, "TS_AMD_APOB_ERASE_START" }, + { TS_AMD_APOB_WRITE_START, "TS_AMD_APOB_WRITE_START" }, + { TS_AMD_APOB_END, "TS_AMD_APOB_END" }, + { TS_ME_INFORM_DRAM_START, "TS_ME_INFORM_DRAM_START" }, + { TS_ME_INFORM_DRAM_END, "TS_ME_INFORM_DRAM_END" }, + { TS_ME_END_OF_POST_START, "TS_ME_END_OF_POST_START" }, + { TS_ME_END_OF_POST_END, "TS_ME_END_OF_POST_END" }, + { TS_ME_BOOT_STALL_END, "TS_ME_BOOT_STALL_END" }, + { TS_ME_ICC_CONFIG_START, "TS_ME_ICC_CONFIG_START" }, + { TS_ME_HOST_BOOT_PREP_END, "TS_ME_HOST_BOOT_PREP_END" }, + { TS_ME_RECEIVED_CRDA_FROM_PMC, "TS_ME_RECEIVED_CRDA_FROM_PMC" }, + { TS_CSE_FW_SYNC_START, "TS_CSE_FW_SYNC_START" }, + { TS_CSE_FW_SYNC_END, "TS_CSE_FW_SYNC_END" }, + { TS_FSP_MEMORY_INIT_START, "TS_FSP_MEMORY_INIT_START" }, + { TS_FSP_MEMORY_INIT_END, "TS_FSP_MEMORY_INIT_END" }, + { TS_FSP_TEMP_RAM_EXIT_START, "TS_FSP_TEMP_RAM_EXIT_START" }, + { TS_FSP_TEMP_RAM_EXIT_END, "TS_FSP_TEMP_RAM_EXIT_END" }, + { TS_FSP_SILICON_INIT_START, "TS_FSP_SILICON_INIT_START" }, + { TS_FSP_SILICON_INIT_END, "TS_FSP_SILICON_INIT_END" }, + { TS_FSP_ENUMERATE_START, "TS_FSP_ENUMERATE_START" }, + { TS_FSP_ENUMERATE_END, "TS_FSP_ENUMERATE_END" }, + { TS_FSP_FINALIZE_START, "TS_FSP_FINALIZE_START" }, + { TS_FSP_FINALIZE_END, "TS_FSP_FINALIZE_END" }, + { TS_FSP_END_OF_FIRMWARE_START, "TS_FSP_END_OF_FIRMWARE_START" }, + { TS_FSP_END_OF_FIRMWARE_END, "TS_FSP_END_OF_FIRMWARE_END" }, + { TS_FSP_MULTI_PHASE_SI_INIT_START, "TS_FSP_MULTI_PHASE_SI_INIT_START" }, + { TS_FSP_MULTI_PHASE_SI_INIT_END, "TS_FSP_MULTI_PHASE_SI_INIT_END" }, + { TS_FSP_MEMORY_INIT_LOAD, "TS_FSP_MEMORY_INIT_LOAD" }, + { TS_FSP_SILICON_INIT_LOAD, "TS_FSP_SILICON_INIT_LOAD" }, + { TS_ME_ROM_START, "TS_ME_ROM_START" }, + { TS_DC_START, "TS_DC_START" }, + { TS_RO_PARAMS_INIT, "TS_RO_PARAMS_INIT" }, + { TS_RO_VB_INIT, "TS_RO_VB_INIT" }, + { TS_RO_VB_SELECT_FIRMWARE, "TS_RO_VB_SELECT_FIRMWARE" }, + { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "TS_RO_VB_SELECT_AND_LOAD_KERNEL" }, + { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "TS_RW_VB_SELECT_AND_LOAD_KERNEL" }, + { TS_VB_SELECT_AND_LOAD_KERNEL, "TS_VB_SELECT_AND_LOAD_KERNEL" }, + { TS_VB_EC_VBOOT_DONE, "TS_VB_EC_VBOOT_DONE" }, + { TS_VB_STORAGE_INIT_DONE, "TS_VB_STORAGE_INIT_DONE" }, + { TS_VB_READ_KERNEL_DONE, "TS_VB_READ_KERNEL_DONE" }, + { TS_VB_VBOOT_DONE, "TS_VB_VBOOT_DONE" }, + { TS_KERNEL_START, "TS_KERNEL_START" }, + { TS_KERNEL_DECOMPRESSION, "TS_KERNEL_DECOMPRESSION" }, +}; + +static const struct timestamp_start_end_pair { + uint32_t id_start; + uint32_t id_end; +} timestamp_start_end_pairs[] = { + { TS_ROMSTAGE_START, TS_ROMSTAGE_END }, + { TS_INITRAM_START, TS_INITRAM_END }, + { TS_VBOOT_START, TS_VBOOT_END }, + { TS_COPYRAM_START, TS_COPYRAM_END }, + { TS_BOOTBLOCK_START, TS_BOOTBLOCK_END }, + { TS_COPYROM_START, TS_COPYROM_END }, + { TS_ULZMA_START, TS_ULZMA_END }, + { TS_ULZ4F_START, TS_ULZ4F_END }, + { TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE }, + { TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE }, + { TS_DEVICE_ENABLE, TS_DEVICE_INITIALIZE }, + { TS_DEVICE_INITIALIZE, TS_DEVICE_DONE }, + { TS_OPROM_INITIALIZE, TS_OPROM_END}, + + { TS_POSTCAR_START, TS_POSTCAR_END }, + { TS_DELAY_START, TS_DELAY_END }, + { TS_READ_UCODE_START, TS_READ_UCODE_END }, + { TS_ELOG_INIT_START, TS_ELOG_INIT_END }, + { TS_COPYVER_START, TS_COPYVER_END }, + { TS_TPMINIT_START, TS_TPMINIT_END }, + { TS_VERIFY_SLOT_START, TS_VERIFY_SLOT_END }, + { TS_HASH_BODY_START, TS_HASH_BODY_END }, + + { TS_TPMPCR_START, TS_TPMPCR_END }, + { TS_TPMLOCK_START, TS_TPMLOCK_END }, + { TS_EC_SYNC_START, TS_EC_SYNC_END }, + + /* Order does matter. From largest to smallest ranges. */ + { TS_COPYVPD_START, TS_COPYVPD_RW_END }, + { TS_COPYVPD_START, TS_COPYVPD_RO_END }, + { TS_COPYVPD_RO_END, TS_COPYVPD_RW_END }, + { TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END }, + + { TS_AGESA_INIT_RESET_START, TS_AGESA_INIT_RESET_END }, + { TS_AGESA_INIT_EARLY_START, TS_AGESA_INIT_EARLY_END }, + { TS_AGESA_INIT_POST_START, TS_AGESA_INIT_POST_END }, + { TS_AGESA_INIT_ENV_START, TS_AGESA_INIT_ENV_END }, + { TS_AGESA_INIT_MID_START, TS_AGESA_INIT_MID_END }, + { TS_AGESA_INIT_LATE_START, TS_AGESA_INIT_LATE_END }, + { TS_AGESA_INIT_RTB_START, TS_AGESA_INIT_RTB_END }, + { TS_AGESA_INIT_RESUME_START, TS_AGESA_INIT_RESUME_END }, + { TS_AGESA_S3_LATE_START, TS_AGESA_S3_LATE_END }, + { TS_AGESA_S3_FINAL_START, TS_AGESA_S3_FINAL_END }, + + { TS_AMD_APOB_READ_START, TS_AMD_APOB_END }, + { TS_AMD_APOB_ERASE_START, TS_AMD_APOB_END }, + { TS_AMD_APOB_WRITE_START, TS_AMD_APOB_END }, + + { TS_ME_INFORM_DRAM_START, TS_ME_INFORM_DRAM_END }, + { TS_ME_END_OF_POST_START, TS_ME_END_OF_POST_END }, + + { TS_CSE_FW_SYNC_START, TS_CSE_FW_SYNC_END }, + { TS_FSP_MEMORY_INIT_START, TS_FSP_MEMORY_INIT_END }, + { TS_FSP_TEMP_RAM_EXIT_START, TS_FSP_TEMP_RAM_EXIT_END }, + { TS_FSP_SILICON_INIT_START, TS_FSP_SILICON_INIT_END }, + { TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END }, + { TS_FSP_FINALIZE_START, TS_FSP_FINALIZE_END }, + { TS_FSP_END_OF_FIRMWARE_START, TS_FSP_END_OF_FIRMWARE_END }, + { TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END }, +}; + #endif diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index a39ef2a..13f8cb3d 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -590,8 +590,139 @@ return 0; } +static int find_matching_end(struct timestamp_table *sorted_tst_p, uint32_t start, uint32_t end) +{ + uint32_t id = sorted_tst_p->entries[start].entry_id; + + for (uint32_t i = start; i < end; i++) { + for (uint32_t k = 0; k < ARRAY_SIZE(timestamp_start_end_pairs); k++) { + if (timestamp_start_end_pairs[k].id_start == id + && timestamp_start_end_pairs[k].id_end + == sorted_tst_p->entries[i].entry_id) + return i; + } + } + + return -1; +} + +static const char *get_timestamp_name(uint32_t id) +{ + for (uint32_t i = 0; i < ARRAY_SIZE(timestamp_enum_ids); i++) + if (timestamp_enum_ids[i].id == id) + return timestamp_enum_ids[i].name; + + return "UNKNOWN"; +} + +static char *new_timestamp_path(const char *parent_path, uint32_t id) +{ + char *new_path; + const char *name = get_timestamp_name(id); + + if (parent_path) { + const size_t parent_path_len = strlen(parent_path); + const size_t name_len = strlen(name); + + new_path = malloc(parent_path_len + 1 + name_len + 1); + memcpy(new_path, parent_path, parent_path_len); + new_path[parent_path_len] = ';'; + memcpy(&new_path[parent_path_len + 1], name, name_len + 1); + } else { + new_path = strdup(name); + } + + return new_path; +} + +static char *new_timestamp_range_path(const char *parent_path, uint32_t start_id, uint32_t end_id) +{ + const char *start_name = get_timestamp_name(start_id); + const char *end_name = get_timestamp_name(end_id); + const size_t start_name_len = strlen(start_name); + const size_t end_name_len = strlen(end_name); + char *new_path; + size_t offset = 0; + + if (parent_path) { + const size_t parent_path_len = strlen(parent_path); + new_path = malloc(parent_path_len + 1 + start_name_len + 1 + end_name_len + 1); + memcpy(new_path, parent_path, parent_path_len); + new_path[parent_path_len] = ';'; + offset = parent_path_len + 1; + } else { + new_path = malloc(start_name_len + 1 + end_name_len + 1); + } + + memcpy(&new_path[offset], start_name, start_name_len); + new_path[offset + start_name_len] = '/'; + memcpy(&new_path[offset + start_name_len + 1], end_name, end_name_len + 1); + + return new_path; +} + +static void process_subrange(struct timestamp_table *sorted_tst_p, uint32_t start, uint32_t end, + const char *parent_path) +{ + for (uint32_t i = start; i < end;) { + const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; + + /* Prepare path to current timestamp */ + char *new_path; + uint64_t stamp; + int match = find_matching_end(sorted_tst_p, i, end); + /* Make all timestamps absolute. */ + stamp = tse->entry_stamp + sorted_tst_p->base_time; + if (match == -1) { + /* Check, if there is a previous timestamp */ + if (i > 0) + stamp = stamp + - (sorted_tst_p->entries[i - 1].entry_stamp + + sorted_tst_p->base_time); + stamp = arch_convert_raw_ts_entry(stamp); + new_path = new_timestamp_path(parent_path, tse->entry_id); + + printf("%s %lu\n", new_path, stamp); + i++; /* Go to next one */ + } else { + const struct timestamp_entry *tse_end = &sorted_tst_p->entries[match]; + stamp = (tse_end->entry_stamp + sorted_tst_p->base_time) - stamp; + stamp = arch_convert_raw_ts_entry(stamp); + new_path = new_timestamp_range_path(parent_path, tse->entry_id, + tse_end->entry_id); + + printf("%s %lu\n", new_path, stamp); + + const int new_start = i + 1; + const int new_end = match; + + if (new_end - new_start > 0) + process_subrange(sorted_tst_p, new_start, new_end, new_path); + + if (find_matching_end(sorted_tst_p, match, end) == -1) + i = match + 1; /* Current range does not start any other one */ + else + i = match; /* End of current range is beginning of another */ + } + + free(new_path); + } +} + +static void dump_timestamps_stacked(struct timestamp_table *sorted_tst_p) +{ + /* Skip first timestamp, as it only marks the start of coreboot execution */ + process_subrange(sorted_tst_p, 1, sorted_tst_p->num_entries, NULL); +} + +enum timestamps_print_type { + TIMESTAMPS_PRINT_NORMAL = 0, + TIMESTAMPS_PRINT_MACHINE_READABLE = 1, + TIMESTAMPS_PRINT_STACKED = 2, +}; + /* dump the timestamp table */ -static void dump_timestamps(int mach_readable) +static void dump_timestamps(enum timestamps_print_type output_type) { const struct timestamp_table *tst_p; struct timestamp_table *sorted_tst_p; @@ -612,7 +743,7 @@ timestamp_set_tick_freq(tst_p->tick_freq_mhz); - if (!mach_readable) + if (output_type == TIMESTAMPS_PRINT_NORMAL) printf("%d entries total:\n\n", tst_p->num_entries); size += tst_p->num_entries * sizeof(tst_p->entries[0]); @@ -644,29 +775,32 @@ */ if (sorted_tst_p->entries[0].entry_stamp < 0) sorted_tst_p->base_time = -sorted_tst_p->entries[0].entry_stamp; - prev_stamp = 0; - total_time = 0; - for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { - uint64_t stamp; - const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; + if (output_type == TIMESTAMPS_PRINT_STACKED) { + dump_timestamps_stacked(sorted_tst_p); + } else { + prev_stamp = 0; + total_time = 0; + for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { + uint64_t stamp; + const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; - /* Make all timestamps absolute. */ - stamp = tse->entry_stamp + sorted_tst_p->base_time; - if (mach_readable) - total_time += - timestamp_print_parseable_entry(tse->entry_id, - stamp, prev_stamp); - else - total_time += timestamp_print_entry(tse->entry_id, - stamp, prev_stamp); - prev_stamp = stamp; - } + /* Make all timestamps absolute. */ + stamp = tse->entry_stamp + sorted_tst_p->base_time; + if (output_type == TIMESTAMPS_PRINT_MACHINE_READABLE) + total_time += timestamp_print_parseable_entry( + tse->entry_id, stamp, prev_stamp); + else if (output_type == TIMESTAMPS_PRINT_NORMAL) + total_time += + timestamp_print_entry(tse->entry_id, stamp, prev_stamp); + prev_stamp = stamp; + } - if (!mach_readable) { - printf("\nTotal Time: "); - print_norm(total_time); - printf("\n"); + if (output_type == TIMESTAMPS_PRINT_NORMAL) { + printf("\nTotal Time: "); + print_norm(total_time); + printf("\n"); + } } unmap_memory(&timestamp_mapping); @@ -1166,6 +1300,7 @@ " -r | --rawdump ID: print rawdump of specific ID (in hex) of cbtable\n" " -t | --timestamps: print timestamp information\n" " -T | --parseable-timestamps: print parseable timestamps\n" + " -S | --stacked-timestamps: print stacked timestamps (e.g. for flame graph tools)\n" " -L | --tcpa-log print TCPA log\n" " -V | --verbose: verbose (debugging) output\n" " -v | --version: print the version\n" @@ -1299,7 +1434,7 @@ int print_rawdump = 0; int print_timestamps = 0; int print_tcpa_log = 0; - int machine_readable_timestamps = 0; + enum timestamps_print_type timestamp_type = TIMESTAMPS_PRINT_NORMAL; enum console_print_type console_type = CONSOLE_PRINT_FULL; unsigned int rawdump_id = 0; int max_loglevel = BIOS_NEVER; @@ -1316,6 +1451,7 @@ {"tcpa-log", 0, 0, 'L'}, {"timestamps", 0, 0, 't'}, {"parseable-timestamps", 0, 0, 'T'}, + {"stacked-timestamps", 0, 0, 'S'}, {"hexdump", 0, 0, 'x'}, {"rawdump", required_argument, 0, 'r'}, {"verbose", 0, 0, 'V'}, @@ -1323,7 +1459,7 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c12B:CltTLxVvh?r:", + while ((opt = getopt_long(argc, argv, "c12B:CltTSLxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1366,11 +1502,17 @@ break; case 't': print_timestamps = 1; + timestamp_type = TIMESTAMPS_PRINT_NORMAL; print_defaults = 0; break; case 'T': print_timestamps = 1; - machine_readable_timestamps = 1; + timestamp_type = TIMESTAMPS_PRINT_MACHINE_READABLE; + print_defaults = 0; + break; + case 'S': + print_timestamps = 1; + timestamp_type = TIMESTAMPS_PRINT_STACKED; print_defaults = 0; break; case 'V': @@ -1483,7 +1625,7 @@ dump_cbmem_raw(rawdump_id); if (print_defaults || print_timestamps) - dump_timestamps(machine_readable_timestamps); + dump_timestamps(timestamp_type); if (print_tcpa_log) dump_tcpa_log(); -- To view, visit https://review.coreboot.org/c/coreboot/+/62474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Gerrit-Change-Number: 62474 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent
by Jakub Czapiga (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Raul Rangel, Jakub Czapiga, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Fred Reitberger, Yu-Ping Wu, Felix Held. Hello build bot (Jenkins), Raul Rangel, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62019 to look at the new patch set (#6). Change subject: timestamps: Rename timestamps to make names more consistent ...................................................................... timestamps: Rename timestamps to make names more consistent This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 --- M src/arch/arm64/romstage.c M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/vpd/vpd.c M src/lib/bootblock.c M src/lib/cbfs.c M src/lib/decompressor.c M src/lib/fit_payload.c M src/lib/hardwaremain.c M src/lib/prog_loaders.c M src/lib/selfboot.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/raminit.c M src/security/vboot/ec_sync.c M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/picasso/romstage.c M src/soc/amd/sabrina/romstage.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/raminit.c M src/soc/intel/common/block/cse/cse_eop.c M src/vendorcode/google/chromeos/cr50_enable_update.c M tests/lib/timestamp-test.c 51 files changed, 273 insertions(+), 273 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62019/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Gerrit-Change-Number: 62019 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/mt8186/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142787): https://review.coreboot.org/c/coreboot/+/62472/comment/0008058b_6d9b4c1d PS1, Line 17: #define NOR_PIN_DRIVE_STRENTH GPIO_DRV3 'STRENTH' may be misspelled - perhaps 'STRENGTH'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142787): https://review.coreboot.org/c/coreboot/+/62472/comment/5dc430ce_4828371b PS1, Line 155: if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0) 'STRENTH' may be misspelled - perhaps 'STRENGTH'? -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:38:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by Shelley Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Ravi kumar. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62370 ) Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Looks like you accidentally uploaded this patch with a new Change Id. Can you please upload as a new patchset to https://review.coreboot.org/c/coreboot/+/61342 and abandon this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/62370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6368e3064548eaead5046b5ca6cd31e1fd498187 Gerrit-Change-Number: 62370 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... soc/medaitek/mt8186: set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/1 diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index d4d3684..f7a376d 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -6,6 +6,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <spi_flash.h> #include <soc/addressmap.h> @@ -13,6 +14,8 @@ #include <soc/gpio.h> #include <soc/spi.h> +#define NOR_PIN_DRIVE_STRENTH GPIO_DRV3 + struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { { .regs = (void *)SPI0_BASE, @@ -147,6 +150,14 @@ for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) { gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select); gpio_set_mode(ptr[i].gpio, ptr[i].func); + + /* Set pin drive to GPIO_DRV3 which is defined as 8mA in MT8186 */ + if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0) + printk(BIOS_WARNING, "%s: failed to set pin drive for %d\n", + __func__, ptr[i].gpio.id); + else + printk(BIOS_INFO, "%s: got pin drive: %#x\n", __func__, + gpio_get_driving(ptr[i].gpio)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 519 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/1 diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 283cf94..cdf0240 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -18,10 +18,50 @@ GPIO_PULL_UP = 1, }; +/* The corresponding value of drive strength is different from different SoCs */ +enum gpio_drv { + GPIO_DRV0 = 0, + GPIO_DRV1 = 1, + GPIO_DRV2 = 2, + GPIO_DRV3 = 3, + GPIO_DRV4 = 4, + GPIO_DRV5 = 5, + GPIO_DRV6 = 6, + GPIO_DRV7 = 7, +}; + +/* + * GPIO DRIVING + * Special IO(I2C, HDMI...) advanced drive strength: + * GPIO_DRV_ADV0: 0.125mA + * GPIO_DRV_ADV1: 0.25mA + * GPIO_DRV_ADV2: 0.5mA + * GPIO_DRV_ADV3: 1mA + */ +enum gpio_drv_adv { + GPIO_DRV_ADV0 = 0, + GPIO_DRV_ADV1 = 1, + GPIO_DRV_ADV2 = 2, + GPIO_DRV_ADV3 = 3, +}; + +struct gpio_drv_info { + int32_t offset; + int8_t shift; + int8_t width; +}; + void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); +/* Normal driving function */ +int gpio_set_driving(gpio_t gpio, enum gpio_drv drv); +int gpio_get_driving(gpio_t gpio); +/* Advanced driving function */ +int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv); +int gpio_get_driving_adv(gpio_t gpio); + enum gpio_irq_type { IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c index bd3ab65..b22a868 100644 --- a/src/soc/mediatek/mt8186/gpio.c +++ b/src/soc/mediatek/mt8186/gpio.c @@ -8,6 +8,388 @@ #include <device/mmio.h> #include <gpio.h> +static const struct gpio_drv_info gpio_driving_info[] = { + [0] = { 0x0, 27, 3, }, + [1] = { 0x0, 27, 3, }, + [2] = { 0x0, 27, 3, }, + [3] = { 0x0, 27, 3, }, + [4] = { 0x10, 0, 3, }, + [5] = { 0x10, 0, 3, }, + [6] = { 0x0, 9, 3, }, + [7] = { 0x0, 9, 3, }, + [8] = { 0x0, 9, 3, }, + [9] = { 0x0, 12, 3, }, + [10] = { 0x0, 0, 3, }, + [11] = { 0x0, 3, 3, }, + [12] = { 0x0, 6, 3, }, + [13] = { 0x0, 0, 3, }, + [14] = { 0x0, 3, 3, }, + [15] = { 0x10, 3, 3, }, + [16] = { 0x10, 3, 3, }, + [17] = { 0x0, 21, 3, }, + [18] = { 0x10, 0, 3, }, + [19] = { 0x0, 27, 3, }, + [20] = { 0x0, 24, 3, }, + [21] = { 0x0, 27, 3, }, + [22] = { 0x0, 24, 3, }, + [23] = { 0x10, 0, 3, }, + [24] = { 0x10, 9, 3, }, + [25] = { 0x10, 0, 3, }, + [26] = { 0x0, 27, 3, }, + [27] = { 0x0, 27, 3, }, + [28] = { 0x10, 0, 3, }, + [29] = { 0x10, 0, 3, }, + [30] = { 0x10, 0, 3, }, + [31] = { 0x10, 3, 3, }, + [32] = { 0x0, 6, 3, }, + [33] = { 0x0, 6, 3, }, + [34] = { 0x0, 3, 3, }, + [35] = { 0x0, 3, 3, }, + [36] = { 0x0, 9, 3, }, + [37] = { 0x0, 9, 3, }, + [38] = { 0x0, 12, 3, }, + [39] = { 0x0, 9, 3, }, + [40] = { 0x0, 15, 3, }, + [41] = { 0x0, 12, 3, }, + [42] = { 0x0, 12, 3, }, + [43] = { 0x0, 12, 3, }, + [44] = { 0x10, 6, 3, }, + [45] = { 0x10, 3, 3, }, + [46] = { 0x10, 3, 3, }, + [47] = { 0x10, 6, 3, }, + [48] = { 0x0, 15, 3, }, + [49] = { 0x0, 15, 3, }, + [50] = { 0x0, 15, 3, }, + [51] = { 0x0, 18, 3, }, + [52] = { 0x10, 3, 3, }, + [53] = { 0x10, 6, 3, }, + [54] = { 0x10, 3, 3, }, + [55] = { 0x10, 3, 3, }, + [56] = { 0x10, 3, 3, }, + [57] = { 0x10, 6, 3, }, + [58] = { 0x10, 6, 3, }, + [59] = { 0x10, 3, 3, }, + [60] = { 0x0, 24, 3, }, + [61] = { 0x0, 24, 3, }, + [62] = { 0x0, 24, 3, }, + [63] = { 0x0, 24, 3, }, + [64] = { 0x0, 27, 3, }, + [65] = { 0x0, 27, 3, }, + [66] = { 0x0, 27, 3, }, + [67] = { 0x10, 0, 3, }, + [68] = { 0x0, 0, 3, }, + [69] = { 0x0, 3, 3, }, + [70] = { 0x10, 3, 3, }, + [71] = { 0x0, 6, 3, }, + [72] = { 0x0, 9, 3, }, + [73] = { 0x0, 12, 3, }, + [74] = { 0x0, 15, 3, }, + [75] = { 0x0, 18, 3, }, + [76] = { 0x0, 21, 3, }, + [77] = { 0x0, 24, 3, }, + [78] = { 0x0, 27, 3, }, + [79] = { 0x0, 24, 3, }, + [80] = { 0x0, 24, 3, }, + [81] = { 0x0, 21, 3, }, + [82] = { 0x0, 21, 3, }, + [83] = { 0x10, 3, 3, }, + [84] = { 0x0, 6, 3, }, + [85] = { 0x0, 9, 3, }, + [86] = { 0x0, 12, 3, }, + [87] = { 0x0, 15, 3, }, + [88] = { 0x0, 18, 3, }, + [89] = { 0x0, 21, 3, }, + [90] = { 0x0, 27, 3, }, + [91] = { 0x10, 0, 3, }, + [92] = { 0x10, 0, 3, }, + [93] = { 0x10, 0, 3, }, + [94] = { 0x10, 0, 3, }, + [95] = { 0x10, 3, 3, }, + [96] = { 0x0, 9, 3, }, + [97] = { 0x0, 6, 3, }, + [98] = { 0x0, 3, 3, }, + [99] = { 0x0, 18, 3, }, + [100] = { 0x0, 18, 3, }, + [101] = { 0x0, 21, 3, }, + [102] = { 0x0, 21, 3, }, + [103] = { 0x0, 21, 3, }, + [104] = { 0x0, 21, 3, }, + [105] = { 0x0, 24, 3, }, + [106] = { 0x0, 24, 3, }, + [107] = { 0x0, 24, 3, }, + [108] = { 0x0, 24, 3, }, + [109] = { 0x0, 27, 3, }, + [110] = { 0x0, 27, 3, }, + [111] = { 0x0, 27, 3, }, + [112] = { 0x0, 27, 3, }, + [113] = { 0x10, 0, 3, }, + [114] = { 0x10, 0, 3, }, + [115] = { 0x10, 6, 3, }, + [116] = { 0x10, 9, 3, }, + [117] = { 0x10, 6, 3, }, + [118] = { 0x10, 6, 3, }, + [119] = { 0x0, 18, 3, }, + [120] = { 0x0, 9, 3, }, + [121] = { 0x0, 12, 3, }, + [122] = { 0x0, 15, 3, }, + [123] = { 0x0, 21, 3, }, + [124] = { 0x0, 0, 3, }, + [125] = { 0x0, 3, 3, }, + [126] = { 0x0, 6, 3, }, + [127] = { 0x10, 12, 3, }, + [128] = { 0x10, 18, 3, }, + [129] = { 0x10, 12, 3, }, + [130] = { 0x10, 18, 3, }, + [131] = { 0x10, 15, 3, }, + [132] = { 0x10, 21, 3, }, + [133] = { 0x10, 15, 3, }, + [134] = { 0x10, 21, 3, }, + [135] = { 0x10, 6, 3, }, + [136] = { 0x10, 15, 3, }, + [137] = { 0x10, 18, 3, }, + [138] = { 0x10, 24, 3, }, + [139] = { 0x0, 21, 3, }, + [140] = { 0x0, 24, 3, }, + [141] = { 0x10, 15, 3, }, + [142] = { 0x10, 21, 3, }, + [143] = { 0x10, 9, 3, }, + [144] = { 0x10, 18, 3, }, + [145] = { 0x10, 12, 3, }, + [146] = { 0x10, 21, 3, }, + [147] = { 0x0, 12, 3, }, + [148] = { 0x0, 12, 3, }, + [149] = { 0x0, 12, 3, }, + [150] = { 0x0, 15, 3, }, + [151] = { 0x0, 15, 3, }, + [152] = { 0x0, 9, 3, }, + [153] = { 0x0, 15, 3, }, + [154] = { 0x0, 15, 3, }, + [155] = { 0x0, 18, 3, }, + [156] = { 0x0, 18, 3, }, + [157] = { 0x0, 0, 3, }, + [158] = { 0x0, 0, 3, }, + [159] = { 0x0, 0, 3, }, + [160] = { 0x0, 0, 3, }, + [161] = { 0x0, 6, 3, }, + [162] = { 0x0, 3, 3, }, + [163] = { 0x10, 12, 3, }, + [164] = { -1, -1, -1}, + [165] = { 0x10, 6, 3, }, + [166] = { 0x10, 6, 3, }, + [167] = { 0x10, 9, 3, }, + [168] = { 0x10, 6, 3, }, + [169] = { 0x10, 12, 3, }, + [170] = { 0x10, 9, 3, }, + [171] = { 0x10, 9, 3, }, + [172] = { 0x10, 9, 3, }, + [173] = { 0x10, 6, 3, }, + [174] = { 0x0, 9, 3, }, + [175] = { 0x0, 12, 3, }, + [176] = { 0x0, 0, 3, }, + [177] = { 0x0, 3, 3, }, + [178] = { 0x0, 6, 3, }, + [179] = { 0x0, 15, 3, }, + [180] = { 0x0, 18, 3, }, + [181] = { 0x0, 21, 3, }, + [182] = { 0x0, 24, 3, }, + [183] = { 0x0, 27, 3, }, + [184] = { 0x10, 0, 3, }, +}; + +_Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM, + "gpio_driving_info array size not match"); + +static const struct gpio_drv_info gpio_driving_adv_info[] = { + [0] = { -1, -1, -1, }, + [1] = { -1, -1, -1, }, + [2] = { -1, -1, -1, }, + [3] = { -1, -1, -1, }, + [4] = { -1, -1, -1, }, + [5] = { -1, -1, -1, }, + [6] = { -1, -1, -1, }, + [7] = { -1, -1, -1, }, + [8] = { -1, -1, -1, }, + [9] = { -1, -1, -1, }, + [10] = { -1, -1, -1, }, + [11] = { -1, -1, -1, }, + [12] = { -1, -1, -1, }, + [13] = { -1, -1, -1, }, + [14] = { -1, -1, -1, }, + [15] = { -1, -1, -1, }, + [16] = { -1, -1, -1, }, + [17] = { -1, -1, -1, }, + [18] = { -1, -1, -1, }, + [19] = { -1, -1, -1, }, + [20] = { -1, -1, -1, }, + [21] = { -1, -1, -1, }, + [22] = { -1, -1, -1, }, + [23] = { -1, -1, -1, }, + [24] = { -1, -1, -1, }, + [25] = { -1, -1, -1, }, + [26] = { -1, -1, -1, }, + [27] = { -1, -1, -1, }, + [28] = { -1, -1, -1, }, + [29] = { -1, -1, -1, }, + [30] = { -1, -1, -1, }, + [31] = { -1, -1, -1, }, + [32] = { -1, -1, -1, }, + [33] = { -1, -1, -1, }, + [34] = { -1, -1, -1, }, + [35] = { -1, -1, -1, }, + [36] = { -1, -1, -1, }, + [37] = { -1, -1, -1, }, + [38] = { -1, -1, -1, }, + [39] = { -1, -1, -1, }, + [40] = { -1, -1, -1, }, + [41] = { -1, -1, -1, }, + [42] = { -1, -1, -1, }, + [43] = { -1, -1, -1, }, + [44] = { -1, -1, -1, }, + [45] = { -1, -1, -1, }, + [46] = { -1, -1, -1, }, + [47] = { -1, -1, -1, }, + [48] = { -1, -1, -1, }, + [49] = { -1, -1, -1, }, + [50] = { -1, -1, -1, }, + [51] = { -1, -1, -1, }, + [52] = { -1, -1, -1, }, + [53] = { -1, -1, -1, }, + [54] = { -1, -1, -1, }, + [55] = { -1, -1, -1, }, + [56] = { -1, -1, -1, }, + [57] = { -1, -1, -1, }, + [58] = { -1, -1, -1, }, + [59] = { -1, -1, -1, }, + [60] = { -1, -1, -1, }, + [61] = { -1, -1, -1, }, + [62] = { -1, -1, -1, }, + [63] = { -1, -1, -1, }, + [64] = { -1, -1, -1, }, + [65] = { -1, -1, -1, }, + [66] = { -1, -1, -1, }, + [67] = { -1, -1, -1, }, + [68] = { -1, -1, -1, }, + [69] = { -1, -1, -1, }, + [70] = { -1, -1, -1, }, + [71] = { -1, -1, -1, }, + [72] = { -1, -1, -1, }, + [73] = { -1, -1, -1, }, + [74] = { -1, -1, -1, }, + [75] = { -1, -1, -1, }, + [76] = { -1, -1, -1, }, + [77] = { -1, -1, -1, }, + [78] = { -1, -1, -1, }, + [79] = { -1, -1, -1, }, + [80] = { -1, -1, -1, }, + [81] = { -1, -1, -1, }, + [82] = { -1, -1, -1, }, + [83] = { -1, -1, -1, }, + [84] = { -1, -1, -1, }, + [85] = { -1, -1, -1, }, + [86] = { -1, -1, -1, }, + [87] = { -1, -1, -1, }, + [88] = { -1, -1, -1, }, + [89] = { -1, -1, -1, }, + [90] = { -1, -1, -1, }, + [91] = { -1, -1, -1, }, + [92] = { -1, -1, -1, }, + [93] = { -1, -1, -1, }, + [94] = { -1, -1, -1, }, + [95] = { -1, -1, -1, }, + [96] = { -1, -1, -1, }, + [97] = { -1, -1, -1, }, + [98] = { -1, -1, -1, }, + [99] = { -1, -1, -1, }, + [100] = { -1, -1, -1, }, + [101] = { -1, -1, -1, }, + [102] = { -1, -1, -1, }, + [103] = { -1, -1, -1, }, + [104] = { -1, -1, -1, }, + [105] = { -1, -1, -1, }, + [106] = { -1, -1, -1, }, + [107] = { -1, -1, -1, }, + [108] = { -1, -1, -1, }, + [109] = { -1, -1, -1, }, + [110] = { -1, -1, -1, }, + [111] = { -1, -1, -1, }, + [112] = { -1, -1, -1, }, + [113] = { -1, -1, -1, }, + [114] = { -1, -1, -1, }, + [115] = { -1, -1, -1, }, + [116] = { -1, -1, -1, }, + [117] = { -1, -1, -1, }, + [118] = { -1, -1, -1, }, + [119] = { -1, -1, -1, }, + [120] = { -1, -1, -1, }, + [121] = { -1, -1, -1, }, + [122] = { -1, -1, -1, }, + [123] = { -1, -1, -1, }, + [124] = { -1, -1, -1, }, + [125] = { -1, -1, -1, }, + [126] = { -1, -1, -1, }, + [127] = { 0x30, 0, 3, }, + [128] = { 0x30, 6, 3, }, + [129] = { 0x30, 0, 3, }, + [130] = { 0x30, 6, 3, }, + [131] = { 0x30, 3, 3, }, + [132] = { 0x30, 9, 3, }, + [133] = { 0x30, 0, 3, }, + [134] = { 0x30, 6, 3, }, + [135] = { 0x20, 0, 3, }, + [136] = { 0x20, 9, 3, }, + [137] = { 0x30, 3, 3, }, + [138] = { 0x30, 9, 3, }, + [139] = { 0x20, 0, 3, }, + [140] = { 0x20, 3, 3, }, + [141] = { 0x30, 3, 3, }, + [142] = { 0x30, 9, 3, }, + [143] = { 0x20, 3, 3, }, + [144] = { 0x20, 12, 3, }, + [145] = { 0x20, 6, 3, }, + [146] = { 0x20, 15, 3, }, + [147] = { -1, -1, -1, }, + [148] = { -1, -1, -1, }, + [149] = { -1, -1, -1, }, + [150] = { -1, -1, -1, }, + [151] = { -1, -1, -1, }, + [152] = { -1, -1, -1, }, + [153] = { -1, -1, -1, }, + [154] = { -1, -1, -1, }, + [155] = { -1, -1, -1, }, + [156] = { -1, -1, -1, }, + [157] = { -1, -1, -1, }, + [158] = { -1, -1, -1, }, + [159] = { -1, -1, -1, }, + [160] = { -1, -1, -1, }, + [161] = { -1, -1, -1, }, + [162] = { -1, -1, -1, }, + [163] = { -1, -1, -1, }, + [164] = { -1, -1, -1, }, + [165] = { -1, -1, -1, }, + [166] = { -1, -1, -1, }, + [167] = { -1, -1, -1, }, + [168] = { -1, -1, -1, }, + [169] = { -1, -1, -1, }, + [170] = { -1, -1, -1, }, + [171] = { -1, -1, -1, }, + [172] = { -1, -1, -1, }, + [173] = { -1, -1, -1, }, + [174] = { -1, -1, -1, }, + [175] = { -1, -1, -1, }, + [176] = { -1, -1, -1, }, + [177] = { -1, -1, -1, }, + [178] = { -1, -1, -1, }, + [179] = { -1, -1, -1, }, + [180] = { -1, -1, -1, }, + [181] = { -1, -1, -1, }, + [182] = { -1, -1, -1, }, + [183] = { -1, -1, -1, }, + [184] = { -1, -1, -1, }, +}; + +_Static_assert(ARRAY_SIZE(gpio_driving_adv_info) == GPIO_NUM, + "gpio_driving_adv_info array size not match"); + static void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; @@ -95,3 +477,98 @@ else gpio_set_pull_pu_pd(gpio, enable, select); } + +static inline bool is_valid_drv(enum gpio_drv drv) +{ + return (drv <= GPIO_DRV7 && drv >= GPIO_DRV0); +} + +static inline bool is_valid_drv_adv(enum gpio_drv_adv drv) +{ + return (drv <= GPIO_DRV_ADV3 && drv >= GPIO_DRV_ADV0); +} + +int gpio_set_driving(gpio_t gpio, enum gpio_drv drv) +{ + uint32_t mask; + const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg, *reg_adv; + + if (!is_valid_drv(drv)) + return -1; + + reg = gpio_find_reg_addr(gpio) + info->offset; + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + + if (info->shift == -1) + return -1; + + mask = BIT(info->width) - 1; + /* Check setting value is not beyond width */ + if ((uint32_t)drv > mask) + return -1; + + clrsetbits32(reg, mask << info->shift, drv << info->shift); + + /* Disable EH if supported */ + if (adv_info->shift != -1) + clrbits32(reg_adv, BIT(adv_info->shift)); + + return 0; +} + +int gpio_get_driving(gpio_t gpio) +{ + const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; + void *reg; + + reg = gpio_find_reg_addr(gpio) + info->offset; + if (info->shift == -1) + return -1; + + return (read32(reg) >> info->shift) & (BIT(info->width) - 1); +} + +int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv) +{ + uint32_t mask; + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg_adv; + + if (!is_valid_drv_adv(drv)) + return -1; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + + if (adv_info->shift == -1) + return -1; + + /* Not include EH bit (the lowest bit) */ + if ((uint32_t)drv > (BIT(adv_info->width - 1) - 1)) + return -1; + + mask = BIT(adv_info->width) - 1; + /* EH enable */ + drv = (drv << 1) | BIT(0); + + clrsetbits32(reg_adv, mask << adv_info->shift, drv << adv_info->shift); + + return 0; +} + +int gpio_get_driving_adv(gpio_t gpio) +{ + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg_adv; + uint32_t drv; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + if (adv_info->shift == -1) + return -1; + + drv = (read32(reg_adv) >> adv_info->shift) & (BIT(adv_info->width) - 1); + + /* Drop EH bit */ + return drv >> 1; +} diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index a47d27c..628b482 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -12,6 +12,8 @@ #include <soc/gpio_common.h> #include <types.h> +#define GPIO_NUM 185 + enum { MAX_GPIO_REG_BITS = 32, MAX_GPIO_MODE_PER_REG = 8, -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Casper Chang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Subrata Banik, Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62465 ) Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > if eMMC sequence diagram expects it to go low on every boot then we can do the same in early gpio ta […] Thanks EricR and Subrata's comment. I set GPP_B3 to low in early table as BH799BB's power on sequence requested. -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:22:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Casper Chang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai, Casper Chang. Hello build bot (Jenkins), Subrata Banik, Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62465 to look at the new patch set (#4). Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE
by EricR Lai (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 ) Change subject: mb, soc: Add the SPD_CACHE_ENABLE ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Gerrit-Change-Number: 62294 Gerrit-PatchSet: 5 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:10:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Change DDR4 Interleave to Non-Interleave
by Zoey Wu (Code Review) 01 Mar '22

01 Mar '22

Zoey Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62469 ) Change subject: Change DDR4 Interleave to Non-Interleave ...................................................................... Change DDR4 Interleave to Non-Interleave Signed-off-by: zoey wu <zoey_wu(a)wistron.corp-partner.google.com> Change-Id: I2e84927b7296c565e6be25b09c5f64a338af51d0 --- A src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/memory.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/62469/1 diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc new file mode 100644 index 0000000..f5c5897 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c new file mode 100644 index 0000000..20ec20b --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/memory.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + + .ddr_config = { + .dq_pins_interleaved = false, + }, + +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/62469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e84927b7296c565e6be25b09c5f64a338af51d0 Gerrit-Change-Number: 62469 Gerrit-PatchSet: 1 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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