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Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
Patch Set 1:
(2 comments)
File src/soc/mediatek/mt8186/spi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142787):
https://review.coreboot.org/c/coreboot/+/62472/comment/0008058b_6d9b4c1d
PS1, Line 17: #define NOR_PIN_DRIVE_STRENTH GPIO_DRV3
'STRENTH' may be misspelled - perhaps 'STRENGTH'?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142787):
https://review.coreboot.org/c/coreboot/+/62472/comment/5dc430ce_4828371b
PS1, Line 155: if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0)
'STRENTH' may be misspelled - perhaps 'STRENGTH'?
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Looks like you accidentally uploaded this patch with a new Change Id. Can you please upload as a new patchset to https://review.coreboot.org/c/coreboot/+/61342 and abandon this one?
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Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
---
M src/soc/mediatek/mt8186/spi.c
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/1
diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c
index d4d3684..f7a376d 100644
--- a/src/soc/mediatek/mt8186/spi.c
+++ b/src/soc/mediatek/mt8186/spi.c
@@ -6,6 +6,7 @@
*/
#include <assert.h>
+#include <console/console.h>
#include <device/mmio.h>
#include <spi_flash.h>
#include <soc/addressmap.h>
@@ -13,6 +14,8 @@
#include <soc/gpio.h>
#include <soc/spi.h>
+#define NOR_PIN_DRIVE_STRENTH GPIO_DRV3
+
struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
{
.regs = (void *)SPI0_BASE,
@@ -147,6 +150,14 @@
for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) {
gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
gpio_set_mode(ptr[i].gpio, ptr[i].func);
+
+ /* Set pin drive to GPIO_DRV3 which is defined as 8mA in MT8186 */
+ if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0)
+ printk(BIOS_WARNING, "%s: failed to set pin drive for %d\n",
+ __func__, ptr[i].gpio.id);
+ else
+ printk(BIOS_INFO, "%s: got pin drive: %#x\n", __func__,
+ gpio_get_driving(ptr[i].gpio));
}
}
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Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> if eMMC sequence diagram expects it to go low on every boot then we can do the same in early gpio ta […]
Thanks EricR and Subrata's comment. I set GPP_B3 to low in early table as BH799BB's power on sequence requested.
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Hello build bot (Jenkins), Subrata Banik, Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage
lost after warm reboot.
Config GPP_B3 unlocked to make reboot works on primus.
BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
test reboot 30 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/4
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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/romstage.c:
https://review.coreboot.org/c/coreboot/+/62294/comment/a7ffa0ef_5d12ae0f
PS4, Line 25: if (dimms_changed) {
> that work too.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb, soc: Add the SPD_CACHE_ENABLE
......................................................................
mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org>
---
M src/mainboard/google/brya/romstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/shadowmountain/romstage.c
M src/mainboard/prodrive/atlas/romstage_fsp_params.c
M src/soc/intel/alderlake/include/soc/meminit.h
M src/soc/intel/alderlake/meminit.c
M src/soc/intel/common/block/include/intelblocks/meminit.h
M src/soc/intel/common/block/memory/Kconfig
M src/soc/intel/common/block/memory/meminit.c
M src/soc/intel/tigerlake/meminit.c
10 files changed, 80 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62294/5
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