coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62472 to look at the new patch set (#3). Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... soc/medaitek/mt8186: set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62471 to look at the new patch set (#3). Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. Value of drive strength is different from different SoCs, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 519 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62472 to look at the new patch set (#2). Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... soc/medaitek/mt8186: set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62471 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. Value of drive strength is different from different SoCs, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 02/04/06/08/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 519 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/cbmem: Add FlameGraph-compatible timestamps output
by Jakub Czapiga (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Jakub Czapiga, Tim Wawrzynczak, Alex Levin, Julius Werner, Jan Dabros. Hello build bot (Jenkins), Tim Wawrzynczak, Alex Levin, Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62474 to look at the new patch set (#2). Change subject: util/cbmem: Add FlameGraph-compatible timestamps output ...................................................................... util/cbmem: Add FlameGraph-compatible timestamps output Flame graphs are used to visualize hierarchical data, like call stacks. Timestamps collected by coreboot can be processed to resemble profiler-like output, and thus can be feed to flame graph generation tools. TEST=Run on coreboot-enabled device and extract timestamps using -t/-T/-S options Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 --- M src/commonlib/include/commonlib/timestamp_serialized.h M util/cbmem/cbmem.c 2 files changed, 368 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62474/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Gerrit-Change-Number: 62474 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by EricR Lai (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak, Casper Chang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62465 ) Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:50:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/cbmem: Add FlameGraph-compatible timestamps output
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62474 ) Change subject: util/cbmem: Add FlameGraph-compatible timestamps output ...................................................................... Patch Set 1: (2 comments) File util/cbmem/cbmem.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142789): https://review.coreboot.org/c/coreboot/+/62474/comment/a0d68e09_a6515a4b PS1, Line 638: static char *new_timestamp_range_path(const char *parent_path, uint32_t start_id, uint32_t end_id) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142789): https://review.coreboot.org/c/coreboot/+/62474/comment/73340bc2_6c21dbad PS1, Line 656: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Gerrit-Change-Number: 62474 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Furquan Shaikh, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/b64e361e_47db87c0 PS9, Line 108: pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR; : } > The "void pointer arithmetic" Arthur is referring to is the sum, because `pcie_ctrl->base` is of typ […] Thanks for your suggestions. But I found the 'read32p' and 'write32p' function is defined in 'src/arch/x86/include/arch/mmio.h', and it cannot be used in ARM platform. I'd like to move these functions to 'src/include/device/mmio.h', what do you think? Do you have any suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:48:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Subrata Banik (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai, Casper Chang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62465 ) Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS3: > Thanks EricR and Subrata's comment. I set GPP_B3 to low in early table as BH799BB's power on sequence requested. Thanks Casper, please update the commit msg to reflect the same as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:42:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent
by Jakub Czapiga (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Raul Rangel, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Fred Reitberger, Yu-Ping Wu, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62019 ) Change subject: timestamps: Rename timestamps to make names more consistent ...................................................................... Patch Set 6: (2 comments) File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/c/coreboot/+/62019/comment/07fc6203_a45e714e PS5, Line 114: TS_ME_INFORM_DRAM_WAIT = 940, : TS_ME_INFORM_DRAM_DONE = 941, > Sure I think that makes sense, they mark the beginning and end of sending DRAM_INIT_DONE to the ME f […] Done File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/c/coreboot/+/62019/comment/cd7bf901_06e049e8 PS3, Line 39: TS_DEVICE_ENUMERATE = 30, : TS_DEVICE_CONFIGURE = 40, : TS_DEVICE_ENABLE = 50, : TS_DEVICE_INITIALIZE = 60, : TS_OPROM_INITIALIZE = 65, : TS_OPROM_COPY_END = 66, : TS_OPROM_END = 67, : TS_DEVICE_DONE = 70, : TS_CBMEM_POST = 75, : TS_WRITE_TABLES = 80, : TS_FINALIZE_CHIPS = 85, : TS_LOAD_PAYLOAD = 90, : TS_ACPI_WAKE_JUMP = 98, : TS_SELFBOOT_JUMP = 99, > Assuming that switching from one state of device state machine from the next one does not take a sig […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Gerrit-Change-Number: 62019 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:41:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022