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Change subject: Documentation/mainboard: Add QEMU POWER9 to index site
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62451/comment/3d48fa76_a291a83c
PS3, Line 10: add its related documentation to the mainboard index site.
Like I said on CB:62449 I'd explicitly mention the problem being fixed.
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Change subject: Documentation: Fix spelling of "QEMU"
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Patch Set 3: Code-Review+2
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Change subject: Documentation/mainboard: Add Supermicro X9SAE to index site
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62449/comment/73856fc0_ab138576
PS2, Line 10: Thus, add its related documentation to the mainboard index site.
I'd explicitly mention the problem being fixed:
The Supermicro X9SAE target is supported since coreboot version 4.15. Documentation is available in the tree, but it's not referenced from the mainboard index page. Fix that.
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Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
Patch Set 5:
(3 comments)
File src/soc/mediatek/mt8186/spi.c:
https://review.coreboot.org/c/coreboot/+/62472/comment/aabf084b_e5f758bb
PS4, Line 154: /* Set pin drive to GPIO_DRV3 which is defined as 8mA in MT8186 */
> The comment is not needed, as the warning log says the same.
Done
https://review.coreboot.org/c/coreboot/+/62472/comment/8c068797_99004a26
PS4, Line 156: printk(BIOS_WARNING, "%s: failed to set pin drive for %d\n",
> 1. … set to 8 mA … […]
it still works for community between SoC to NOR, but the waveform is not correct
and there maybe are some impact for this situation.
https://review.coreboot.org/c/coreboot/+/62472/comment/883a6b92_6b6f0826
PS4, Line 160: gpio_get_driving(ptr[i].gpio));
> Looks like a debug message?
Done
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Change subject: amdfwtool: Change the some FW's level for A/B recovery
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Now the result Majolica image is unchanged with or without this CL, setting the recovery_ab as 1.
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/88bd5cb4_3c9ec309
PS3, Line 23: GPIO_DRV0 = 0,
> Why not GPIO_DRV_STRENGTH_2_MA to GPIO_DRV_STRENGTH_16_MA, and so on?
Value of drive strength is different from different SoCs, and this is in common driver for all SoCs.
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
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Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
---
M src/soc/mediatek/mt8186/spi.c
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/5
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
Value of drive strength is different from different SoCs, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 519 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/4
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