coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Paul Menzel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62192/comment/c6a85c59_eb35cb12 PS6, Line 11: max 3 times before triggering the error handling flow. What is the problem, and why is the retry needed? Why three and not less or more? Patchset: PS6: Are new debug messages printed? File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62192/comment/f302d1da_500e8d08 PS6, Line 55: case CSE_TX_ERR_CSE_NOT_READY: Does this need fallthrough statements? Does clang build the image without problems? -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:35:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
by Zoey Wu (Code Review) 01 Mar '22

01 Mar '22

Zoey Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62478 ) Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave ...................................................................... mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4. BUG=b:219831754 Signed-off-by: zoey wu <zoey_wu(a)wistron.corp-partner.google.com> Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d --- M src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/memory.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62478/1 diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc index aa151d6..f5c5897 100644 --- a/src/mainboard/google/brya/variants/moli/Makefile.inc +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c new file mode 100644 index 0000000..cf64454 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/memory.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/62478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Gerrit-Change-Number: 62478 Gerrit-PatchSet: 1 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implement error codes for for heci_send_receive()
by Paul Menzel (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Kane Chen, Andrey Petrov, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62299 ) Change subject: soc/intel/common: Implement error codes for for heci_send_receive() ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62299/comment/57c2849a_7db29e45 PS4, Line 17: timeout or Only one space. https://review.coreboot.org/c/coreboot/+/62299/comment/a08ef936_c31e9727 PS4, Line 27: TEST=Build and boot Brya board Could you force the error paths to see if the error codes are used correctly? -- To view, visit https://review.coreboot.org/c/coreboot/+/62299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Gerrit-Change-Number: 62299 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
by Casper Chang (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Terry Chen, Malik Hsu, Tim Wawrzynczak, Casper Chang. Hello build bot (Jenkins), Subrata Banik, Terry Chen, Malik Hsu, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62465 to look at the new patch set (#5). Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked ...................................................................... mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. Also set GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power on sequence. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62465/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Gerrit-Change-Number: 62465 Gerrit-PatchSet: 5 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kinox: update gpio settings
by Dtrain Hsu (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Tim Wawrzynczak. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62364 ) Change subject: mb/google/brya/var/kinox: update gpio settings ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/62364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Gerrit-Change-Number: 62364 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:29:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 3: Verified+1 (2 comments) File src/soc/mediatek/mt8186/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142792): https://review.coreboot.org/c/coreboot/+/62472/comment/c19fabff_2353f0e7 PS3, Line 17: #define NOR_PIN_DRIVE_STRENTH GPIO_DRV3 'STRENTH' may be misspelled - perhaps 'STRENGTH'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142792): https://review.coreboot.org/c/coreboot/+/62472/comment/4b8b1af6_c6d4ae28 PS3, Line 155: if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0) 'STRENTH' may be misspelled - perhaps 'STRENGTH'? -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:17:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Raihow Shi (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 5: (4 comments) This change is ready for review. File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62321/comment/c874b112_c146300c PS2, Line 30: register "wake" = "GPE0_PME_B0" : device generic 0 on end > nit: one too many tabs here, remove extra one please done https://review.coreboot.org/c/coreboot/+/62321/comment/4abe53b7_d549a02a PS2, Line 79: chip soc/intel/common/block/pcie/rtd3 : register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" : register "srcclk_pin" = "1" : device generic 0 alias emmc_rtd3 on end : end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1 > please indent this section by one more tab done https://review.coreboot.org/c/coreboot/+/62321/comment/24a08bd3_11e66af3 PS2, Line 125: register "group" = "ACPI_PLD_GROUP(1, 1)" > We are switching to using a more fully-specified _PLD object, can you please update this to match? S […] done https://review.coreboot.org/c/coreboot/+/62321/comment/dbe76f7e_b8393c34 PS2, Line 196: > tab please done -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 5 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 2: Verified+1 (2 comments) File src/soc/mediatek/mt8186/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142791): https://review.coreboot.org/c/coreboot/+/62472/comment/8bc021cf_7dbf6a1a PS2, Line 17: #define NOR_PIN_DRIVE_STRENTH GPIO_DRV3 'STRENTH' may be misspelled - perhaps 'STRENGTH'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142791): https://review.coreboot.org/c/coreboot/+/62472/comment/3e6cc710_5bc13960 PS2, Line 155: if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0) 'STRENTH' may be misspelled - perhaps 'STRENGTH'? -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 09:06:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 4: (2 comments) File src/soc/mediatek/mt8186/spi.c: https://review.coreboot.org/c/coreboot/+/62472/comment/5088128c_7ebed1b1 PS1, Line 17: #define NOR_PIN_DRIVE_STRENTH GPIO_DRV3 > 'STRENTH' may be misspelled - perhaps 'STRENGTH'? Please fix. https://review.coreboot.org/c/coreboot/+/62472/comment/0edcb7a0_f6556356 PS1, Line 155: if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0) > 'STRENTH' may be misspelled - perhaps 'STRENGTH'? Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 08:59:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62472 to look at the new patch set (#4). Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... soc/medaitek/mt8186: set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022