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I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
......................................................................
soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.
This implementation is according to chapter 5.13 in MT8186 Functional
Specification.
BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
---
M src/soc/mediatek/mt8186/include/soc/rtc.h
M src/soc/mediatek/mt8186/rtc.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/62290/8
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to look at the new patch set (#2).
Change subject: soc/mediatek: remove unused RTC_GPIO_USER_MASK
......................................................................
soc/mediatek: remove unused RTC_GPIO_USER_MASK
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
---
M src/soc/mediatek/common/rtc_mt6359p.c
M src/soc/mediatek/mt8173/rtc.c
M src/soc/mediatek/mt8183/rtc.c
M src/soc/mediatek/mt8186/rtc.c
4 files changed, 0 insertions(+), 8 deletions(-)
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Hello build bot (Jenkins), Raul Rangel, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Fred Reitberger, Yu-Ping Wu, Felix Held,
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Change subject: timestamps: Rename timestamps to make names more consistent
......................................................................
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
---
M src/arch/arm64/romstage.c
M src/arch/x86/postcar.c
M src/arch/x86/postcar_loader.c
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/vpd/vpd.c
M src/lib/bootblock.c
M src/lib/cbfs.c
M src/lib/decompressor.c
M src/lib/fit_payload.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/selfboot.c
M src/mainboard/google/daisy/romstage.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/peach_pit/romstage.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/raminit.c
M src/security/vboot/ec_sync.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/pi/agesawrapper.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/sabrina/romstage.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
M tests/lib/timestamp-test.c
51 files changed, 274 insertions(+), 274 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62019/7
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: amdfwtool: Check the length of matching string before accessing
......................................................................
amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.
Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/62483/1
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 7f9816b..fc3e6fa 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -532,7 +532,8 @@
if (cb_config->recovery_ab == 0)
ch_lvl = oneline[match[3].rm_so + 1];
else
- ch_lvl = oneline[match[3].rm_so + 2];
+ if ((match[3].rm_eo - match[3].rm_so) >= 3)
+ ch_lvl = oneline[match[3].rm_so + 2];
}
if (find_register_fw_filename_psp_dir(
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62482
to review the following change.
Change subject: amdfwtool: Clear struct match before regular expression matching
......................................................................
amdfwtool: Clear struct match before regular expression matching
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value.
Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/62482/1
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index a6b73ee..7f9816b 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -428,10 +428,12 @@
return OK;
}
+#define N_MATCHES 4
static int is_valid_entry(char *oneline, regmatch_t *match)
{
int retval;
+ memset (match, 0, sizeof(regmatch_t) * N_MATCHES);
if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) {
oneline[match[1].rm_eo] = '\0';
oneline[match[2].rm_eo] = '\0';
@@ -467,7 +469,6 @@
return retval;
}
-#define N_MATCHES 4
/*
return value:
0: The config file can not be parsed correctly.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Nikolai Vyssotski, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62329
to look at the new patch set (#4).
Change subject: amdfwtool: Change the some FW's level for A/B recovery
......................................................................
amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/fw.cfg
M util/amdfwtool/amdfwtool.c
2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/62329/4
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Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
......................................................................
Set Ready For Review
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Change subject: soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
......................................................................
Patch Set 4:
(3 comments)
File src/soc/mediatek/mt8186/spi.c:
https://review.coreboot.org/c/coreboot/+/62472/comment/9517faec_10d6d8e5
PS4, Line 154: /* Set pin drive to GPIO_DRV3 which is defined as 8mA in MT8186 */
The comment is not needed, as the warning log says the same.
https://review.coreboot.org/c/coreboot/+/62472/comment/3cc77118_f4b7c6ee
PS4, Line 156: printk(BIOS_WARNING, "%s: failed to set pin drive for %d\n",
1. … set to 8 mA …
2. What won’t work, when it’s set incorrectly?
https://review.coreboot.org/c/coreboot/+/62472/comment/b2fdb1b7_2e2370e1
PS4, Line 160: gpio_get_driving(ptr[i].gpio));
Looks like a debug message?
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Change subject: mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62465/comment/78c142e8_77fdd53e
PS4, Line 9: With GPP_B3 locked, primus eMMC SKU encounter eMMC storage
: lost after warm reboot.
: Config GPP_B3 unlocked to make reboot works on primus.
Please reflow for 72 characters per line, and either add exactly one blank line between paragraphs, or do not break lines after the end of sentences.
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