coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 1: (1 comment) File src/drivers/gfx/nvidia/optimus/optimus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142823): https://review.coreboot.org/c/coreboot/+/62496/comment/9162a830_0e596263 PS1, Line 261: const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Mar 2022 12:37:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
by build bot (Jenkins) (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62495 ) Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops ...................................................................... Patch Set 1: (13 comments) File src/ec/clevo/it5570/acpi/ec_ram.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/32c5e25b_308d224a PS1, Line 293: Offset (0xF8), trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/e6fafaf0_5ea50ed8 PS1, Line 294: FCMD, 8, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/63116246_00796a2c PS1, Line 295: FDAT, 8, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/21782737_6beacc41 PS1, Line 296: FBUF, 8, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/82d3031f_a171b2e0 PS1, Line 297: FBF1, 8, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/80804a77_494553b0 PS1, Line 298: FBF2, 8, trailing whitespace File src/ec/clevo/it5570/chip.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/8c619870_3374e8f7 PS1, Line 104: /* Depth 2 space is always avaiable, no need for conf mode */ 'avaiable' may be misspelled - perhaps 'available'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/d98fd5a8_a0fdd531 PS1, Line 107: outb(0x2e,0x2e); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/bf89d3d9_0fe82a9b PS1, Line 115: outb(0x2e,0x2e); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/0db626cd_aeec1197 PS1, Line 179: if ( curve.speed[i] < curve.speed[i-1] space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/bd08564f_d4114619 PS1, Line 283: printk (BIOS_ERR, "EC: Fan 0 curve invalid. Check your devicetree.cb.\n"); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/d6009ce5_a5acda06 PS1, Line 291: printk (BIOS_WARNING, "EC: Fan %d curve invalid. Using fan 0 curve.\n", i); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-142822): https://review.coreboot.org/c/coreboot/+/62495/comment/4a22b153_801b84be PS1, Line 291: printk (BIOS_WARNING, "EC: Fan %d curve invalid. Using fan 0 curve.\n", i); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/62495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c7d1d4f86d764bd10cfa3b0da23d1116281f3b Gerrit-Change-Number: 62495 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Tue, 01 Mar 2022 12:37:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NS50 Tiger Lake laptop support
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62499 ) Change subject: mb/clevo/tgl-u: Add Clevo NS50 Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NS50 Tiger Lake laptop support Change-Id: I90ad6ec1c174aa09329b4979205c41a3ec458849 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A configs/config.clevo_ns50mu M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/variants/ns5x/Makefile.inc A src/mainboard/clevo/tgl-u/variants/ns5x/board_info.txt A src/mainboard/clevo/tgl-u/variants/ns5x/data.vbt A src/mainboard/clevo/tgl-u/variants/ns5x/gpio.c A src/mainboard/clevo/tgl-u/variants/ns5x/hda_verb.c A src/mainboard/clevo/tgl-u/variants/ns5x/overridetree.cb 9 files changed, 957 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/62499/1 diff --git a/configs/config.clevo_ns50mu b/configs/config.clevo_ns50mu new file mode 100644 index 0000000..d1f80d5 --- /dev/null +++ b/configs/config.clevo_ns50mu @@ -0,0 +1,30 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_TSEG_STAGE_CACHE=y +CONFIG_VENDOR_CLEVO=y +CONFIG_VBOOT=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Notebook" +CONFIG_BOARD_CLEVO_NS5X=y +CONFIG_PCIEXP_HOTPLUG_BUSES=42 +CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c00000 +CONFIG_USE_PM_ACPI_TIMER=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x30000 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NS50MU" +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_SMMSTORE_V2=y +CONFIG_SMMSTORE_SIZE=0x40000 +# CONFIG_TPM_PPI is not set +CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50 +CONFIG_VBOOT_KEYBLOCK_VERSION=1 +CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_POST_IO_PORT=0x80 +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_CUSTOM=y +CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo" +CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS="-D PLATFORM_BOOT_TIMEOUT=2 -D BOOT_MENU_KEY=0x0011 -D SETUP_MENU_KEY=0x000C -D BOOTLOADER=COREBOOT -D PCIE_BASE=0xc0000000 -DPS2_KEYBOARD_ENABLE -D NETWORK_IPXE=TRUE -D SERIAL_TERMINAL=TRUE -D SECURE_BOOT_ENABLE=TRUE -D TPM_ENABLE=TRUE" diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig index cf422dd..8f4cdc1 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -3,6 +3,10 @@ select BOARD_CLEVO_TGL_U_COMMON select DRIVER_NVIDIA_OPTIMUS +config BOARD_CLEVO_NS5X_BASE + bool "NS5x" + select BOARD_CLEVO_TGL_U_COMMON + config BOARD_CLEVO_TGL_U_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 @@ -35,10 +39,12 @@ config VARIANT_DIR string default "nv4x" if BOARD_CLEVO_NV4X_BASE + default "ns5x" if BOARD_CLEVO_NS5X_BASE config MAINBOARD_PART_NUMBER string default "nv4x" if BOARD_CLEVO_NV4X + default "ns5x" if BOARD_CLEVO_NS5X config MAINBOARD_FAMILY string diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name index 5ea7dcd..dfcdd46 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig.name +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -4,3 +4,7 @@ bool "NV4x" select BOARD_CLEVO_NV4X_BASE +config BOARD_CLEVO_NS5X + bool "NS5x" + select BOARD_CLEVO_NS5X_BASE + diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/Makefile.inc b/src/mainboard/clevo/tgl-u/variants/ns5x/Makefile.inc new file mode 100644 index 0000000..2438407 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/board_info.txt b/src/mainboard/clevo/tgl-u/variants/ns5x/board_info.txt new file mode 100644 index 0000000..7bbda77 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/board_info.txt @@ -0,0 +1 @@ +Board name: NS5x diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/data.vbt b/src/mainboard/clevo/tgl-u/variants/ns5x/data.vbt new file mode 100644 index 0000000..369d07d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/data.vbt Binary files differ diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/gpio.c b/src/mainboard/clevo/tgl-u/variants/ns5x/gpio.c new file mode 100644 index 0000000..e4142ea --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/gpio.c @@ -0,0 +1,647 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, UP_20K, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_CFG_GPO(GPP_B8, 1, DEEP), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + + /* GPP_T2 - GPIO */ + PAD_NC(GPP_T2, NONE), + + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + + /* GPP_A6 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + + /* GPP_A9 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + + /* GPP_A10 - GPIO */ + PAD_NC(GPP_A10, NONE), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - GPIO */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + PAD_NC(GPP_A17, NONE), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + PAD_NC(GPP_A19, NONE), + + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NONE), + + /* GPP_A23 - GPIO */ + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H4 - GPIO */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H10 - SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - GPIO */ + PAD_NC(GPP_H15, NONE), + + /* GPP_H16 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + + /* GPP_D1 - GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + + /* GPP_D2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_U (TGL UP3 only) ------- */ + + /* GPP_U4 - GPIO */ + PAD_CFG_GPO(GPP_U4, 0, PLTRST), + + /* GPP_U5 - GPIO */ + PAD_CFG_GPO(GPP_U5, 1, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, PWROK, OFF, ACPI), + + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 1, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_APIC_HIGH(GPP_C14, UP_20K, DEEP), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + + /* GPP_C17 - I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* GPP_C18 - I2C1_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - GPIO */ + PAD_NC(GPP_F4, NONE), + + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 1, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + + /* GPP_F10 - GPIO */ + PAD_NC(GPP_F10, NONE), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_CFG_GPO(GPP_E1, 0, PLTRST), + + /* GPP_E2 - GPIO */ + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + + /* GPP_E3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - GPIO */ + PAD_NC(GPP_E22, NONE), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/ns5x/hda_verb.c new file mode 100644 index 0000000..d980767 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x155851a1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155851a1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/ns5x/overridetree.cb b/src/mainboard/clevo/tgl-u/variants/ns5x/overridetree.cb new file mode 100644 index 0000000..ad2861e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns5x/overridetree.cb @@ -0,0 +1,222 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + # TODO: Check if this is correct + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Thermal + register "tcc_offset" = "2" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + +# Actual device tree + device domain 0 on + subsystemid 0x1558 0x51a1 inherit + + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" + register "srcclk_pin" = "0" + device generic 0 on end + end + + # Disable Optane hybrid storage mode + register "HybridStorageMode" = "0" + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # USB-A daughterboard + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C motherboard + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB-A motherboard + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint Reader + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # CCD + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + # USB3 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 0) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 1) + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 0)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""Elantech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref sata on + # SATA1 (SSD0) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + register "SataSalpSupport" = "1" + end + device ref pcie_rp5 off end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 2 (CARD) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 3 (GLAN) + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "3" # GLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 1 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[1]" = "7" + register "PcieClkSrcClkReq[1]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 4 (SSD0) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD0"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "4" # SSD0_CLKREQ# + device generic 0 on end + end + end + device ref pch_espi on + chip ec/clevo/it5570 + device pnp 0c09.0 on end + register "fan_mode" = "FAN_MODE_CUSTOM" + register "fans[0].curve.temperature" = "{ 40, 60, 70, 80 }" + register "fans[0].curve.speed" = "{ 16, 25, 50, 100 }" + end + end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/62499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ad6ec1c174aa09329b4979205c41a3ec458849 Gerrit-Change-Number: 62499 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michael Niewöhner. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62498 to review the following change. Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ...................................................................... mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc --- A configs/config.clevo_nv4x M src/ec/clevo/it5570/acpi/ec_ram.asl A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl A src/mainboard/clevo/tgl-u/board.fmd A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.c A src/mainboard/clevo/tgl-u/memory.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/smihandler.c A src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h A src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc A src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt A src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c A src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb A src/mainboard/clevo/tgl-u/vboot-rwa.fmd 27 files changed, 1,242 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/1 diff --git a/configs/config.clevo_nv4x b/configs/config.clevo_nv4x new file mode 100644 index 0000000..020973b --- /dev/null +++ b/configs/config.clevo_nv4x @@ -0,0 +1,30 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_TSEG_STAGE_CACHE=y +CONFIG_VENDOR_CLEVO=y +CONFIG_VBOOT=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Notebook" +CONFIG_BOARD_CLEVO_NV4X=y +CONFIG_PCIEXP_HOTPLUG_BUSES=42 +CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c00000 +CONFIG_USE_PM_ACPI_TIMER=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x30000 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NV4XMB,ME,MZ" +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_SMMSTORE_V2=y +CONFIG_SMMSTORE_SIZE=0x40000 +# CONFIG_TPM_PPI is not set +CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50 +CONFIG_VBOOT_KEYBLOCK_VERSION=1 +CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_POST_IO_PORT=0x80 +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_CUSTOM=y +CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo" +CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS="-D PLATFORM_BOOT_TIMEOUT=2 -D BOOT_MENU_KEY=0x0011 -D SETUP_MENU_KEY=0x000C -D BOOTLOADER=COREBOOT -D PCIE_BASE=0xc0000000 -DPS2_KEYBOARD_ENABLE -D NETWORK_IPXE=TRUE -D SERIAL_TERMINAL=TRUE -D SECURE_BOOT_ENABLE=TRUE -D TPM_ENABLE=TRUE" diff --git a/src/ec/clevo/it5570/acpi/ec_ram.asl b/src/ec/clevo/it5570/acpi/ec_ram.asl index ce8cce0..dd7f0b6 100644 --- a/src/ec/clevo/it5570/acpi/ec_ram.asl +++ b/src/ec/clevo/it5570/acpi/ec_ram.asl @@ -290,12 +290,12 @@ OperationRegion (EC81, EmbeddedControl, Zero, 0xFF) Field (EC81, ByteAcc, Lock, Preserve) { - Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, FBF3, 8 } diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig new file mode 100644 index 0000000..cf422dd --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -0,0 +1,115 @@ +config BOARD_CLEVO_NV4X_BASE + bool "NV4x" + select BOARD_CLEVO_TGL_U_COMMON + select DRIVER_NVIDIA_OPTIMUS + +config BOARD_CLEVO_TGL_U_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select HAVE_SMI_HANDLER + select EC_CLEVO_IT5570 + select TPM_MEASURED_BOOT + +if BOARD_CLEVO_TGL_U_COMMON + +config MAINBOARD_DIR + string + default "clevo/tgl-u" + +config VARIANT_DIR + string + default "nv4x" if BOARD_CLEVO_NV4X_BASE + +config MAINBOARD_PART_NUMBER + string + default "nv4x" if BOARD_CLEVO_NV4X + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware + +config MAX_CPUS + int + default 8 + +config PCIEXP_HOTPLUG + default y + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c00000 # 448 MiB + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config DIMM_MAX + int + default 4 # Hack to make soc code work + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_ALWAYS_ENABLE_DISPLAY + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config UART_FOR_CONSOLE + int + default 2 + +config TPM_PIRQ + hex + default 0x1C # GPP_C14 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +# Getting the console output requires soldering the wires to the mainboard. +# Disable the serial output by default as it won't be commonly used and will +# only make the boot time longer. +config CONSOLE_SERIAL + default n + +endif # BOARD_CLEVO_TGL_U_COMMON diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name new file mode 100644 index 0000000..5ea7dcd --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -0,0 +1,6 @@ +comment "Tiger Lake U" + +config BOARD_CLEVO_NV4X + bool "NV4x" + select BOARD_CLEVO_NV4X_BASE + diff --git a/src/mainboard/clevo/tgl-u/Makefile.inc b/src/mainboard/clevo/tgl-u/Makefile.inc new file mode 100644 index 0000000..f7cc796 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += memory.c +romstage-y += romstage.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/tgl-u/acpi/mainboard.asl b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl new file mode 100644 index 0000000..5e74220 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SLPB 0x6B // PME_STS +#define EC_GPE_LID 0x6B // PME_STS +#define EC_GPE_SCI 0x6E // ESPI_SCI +#define EC_GPE_PWRB 0x43 // GPD9 Power Button +#define EC_GPE_RTC 0x72 // RTC Alarm Status +// echo '\_SB.SLPB._PRW' | sudo tee /proc/acpi/call; sudo cat /proc/acpi/call +// echo '\_SB.PC00.LPCB.EC._GPE' | sudo tee /proc/acpi/call; sudo cat /proc/acpi/call + +Scope (\_SB) { + #include "sleep.asl" + + #include <ec/clevo/it5570/acpi/ac.asl> + #include <ec/clevo/it5570/acpi/battery.asl> + #include <ec/clevo/it5570/acpi/buttons.asl> + #include <ec/clevo/it5570/acpi/lid.asl> + + Scope (PCI0.LPCB) { + #include <ec/clevo/it5570/acpi/ec.asl> + } +} + +Scope (_GPE) { + #include <ec/clevo/it5570/acpi/gpe.asl> +} diff --git a/src/mainboard/clevo/tgl-u/acpi/sleep.asl b/src/mainboard/clevo/tgl-u/acpi/sleep.asl new file mode 100644 index 0000000..bfcb487 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/sleep.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} + +/* + * Display On/Off Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MDSX, 1, Serialized) +{ + If (Arg0 == 1) { + /* Display On */ + \_SB.PCI0.LPCB.EC0.MSFG = Zero + } Else { + /* Display Off */ + If ((\_SB.PCI0.LPCB.EC0.S5FG != One)) + { + \_SB.PCI0.LPCB.EC0.MSFG = One + } + } +} diff --git a/src/mainboard/clevo/tgl-u/board.fmd b/src/mainboard/clevo/tgl-u/board.fmd new file mode 100644 index 0000000..c47e6a4 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/board.fmd @@ -0,0 +1,13 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + FMAP 4K + COREBOOT(CBFS) +} diff --git a/src/mainboard/clevo/tgl-u/board_info.txt b/src/mainboard/clevo/tgl-u/board_info.txt new file mode 100644 index 0000000..5822307 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Clevo +Category: laptop +Release year: 2021 +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/tgl-u/bootblock.c b/src/mainboard/clevo/tgl-u/bootblock.c new file mode 100644 index 0000000..a434521 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/bootblock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "nvidia: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} + +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); + dgpu_power_enable(1); +} diff --git a/src/mainboard/clevo/tgl-u/cmos.default b/src/mainboard/clevo/tgl-u/cmos.default new file mode 100644 index 0000000..39b95be --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +preserve_smmstore=0 diff --git a/src/mainboard/clevo/tgl-u/cmos.layout b/src/mainboard/clevo/tgl-u/cmos.layout new file mode 100644 index 0000000..942a6b3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.layout @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +#395 4 e 3 debug_level +408 1 h 1 preserve_smmstore +984 16 h 0 check_sum + +enumerations + +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/clevo/tgl-u/dsdt.asl b/src/mainboard/clevo/tgl-u/dsdt.asl new file mode 100644 index 0000000..6e5dd9e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/dsdt.asl @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include <acpi/mainboard.asl> +} diff --git a/src/mainboard/clevo/tgl-u/mainboard.c b/src/mainboard/clevo/tgl-u/mainboard.c new file mode 100644 index 0000000..24167c7 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/mainboard.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <intelblocks/lpc_lib.h> +#include <soc/gpio.h> +#include <smbios.h> +#include <string.h> + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + /* Configure MMIO window before FSP-S locks the DMI registers */ + lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570_RAM_BASE, 0x10000); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/clevo/tgl-u/memory.c b/src/mainboard/clevo/tgl-u/memory.c new file mode 100644 index 0000000..e0f01a9 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/memory.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + variant_configure_fspm(mupd); +} diff --git a/src/mainboard/clevo/tgl-u/romstage.c b/src/mainboard/clevo/tgl-u/romstage.c new file mode 100644 index 0000000..be7494e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> + +static const struct mb_cfg variant_mem_config = { + .type = MEM_TYPE_DDR4, + .ect = false, /* Early Command Training */ + .ddr4_config = { + .dq_pins_interleaved = false, + } +}; + +static const struct mem_spd variant_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, +}; + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg *mem_config = &variant_mem_config; + const struct mem_spd *spd_info = &variant_spd_info; + const bool half_populated = false; + + memcfg_init(&memupd->FspmConfig, mem_config, spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + memupd->FspmConfig.VtdDisable = !vtd; + + const uint8_t ht = get_uint_option("hyper_threading", + memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; +} diff --git a/src/mainboard/clevo/tgl-u/smihandler.c b/src/mainboard/clevo/tgl-u/smihandler.c new file mode 100644 index 0000000..26d6438 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/smihandler.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/clevo/it5570/ec.h> +#include <intelblocks/smihandler.h> + +void mainboard_smi_espi_handler(void) +{ + printk(BIOS_DEBUG, "Mainboard SMI eSPI handler\n"); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_DEBUG, "Mainboard SMI sleep handler: %02x\n", slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + printk(BIOS_DEBUG, "Mainboard SMI APMC handler: %02x\n", apmc); + clevo_it5570_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..4281387 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb @@ -0,0 +1,129 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Disable DPTF + register "dptf_enable" = "0" + + # Enable External Bypass + register "external_bypass" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # System Agent dynamic frequency support + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + +# FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # LPM states + register "LpmStateDisableMask" = " + LPM_S0i2_1 | + LPM_S0i2_2 | + LPM_S0i3_1 | + LPM_S0i3_2 | + LPM_S0i3_3 | + LPM_S0i3_4 + " + + # Enable CNVi BT + register "CnviBtCore" = "true" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref heci1 on end + device ref p2sb on end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref pch_espi on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..20ce364 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc b/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc new file mode 100644 index 0000000..2438407 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt b/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt new file mode 100644 index 0000000..8db7db3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt @@ -0,0 +1 @@ +Board name: NV4x diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt b/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt new file mode 100644 index 0000000..369d07d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt Binary files differ diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c b/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c new file mode 100644 index 0000000..8d2f24c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D13, 0, DEEP), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_U (TGL UP3 only) ------- */ + //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ + //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD2, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPD7, 1, RSMRST), + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, DEEP), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 0, PLTRST), + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), /* DGPU_RST#_PCH */ + PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), /* DGPU_PWR_EN */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c new file mode 100644 index 0000000..1979c95 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584019, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb b/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb new file mode 100644 index 0000000..02c5511 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb @@ -0,0 +1,234 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + # TODO: Check if this is correct + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Thermal + register "tcc_offset" = "13" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_C" + register "pmc_gpe0_dw1" = "PMC_GPP_E" + register "pmc_gpe0_dw2" = "PMC_GPD" + +# Actual device tree + device domain 0 on + subsystemid 0x1558 0x4018 inherit + + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + + # Disable Optane hybrid storage mode + register "HybridStorageMode" = "0" + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A port1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB-A port3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Finger + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT USB-C + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # CCD + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port2 (right port, lane 0) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port4 (right port, lane 1) + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c2 on + # Pantone ROM + register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref pcie_rp5 on + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/gfx/nvidia/optimus + register "desc" = ""DGPU"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "2" # PEG_CLKREQ# + register "ec_notify_method" = ""\\_SB.PCI0.LPCB.EC0.DGPM"" + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x1, Clock 3 (CARD) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp10 on + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "4" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + end + device ref pch_espi on + chip ec/clevo/it5570 + device pnp 0c09.0 on end + register "fan_mode" = "FAN_MODE_CUSTOM" + register "fans[0].curve.temperature" = "{ 40, 60, 70, 80 }" + register "fans[0].curve.speed" = "{ 16, 25, 50, 100 }" + register "fans[1].curve.temperature" = "{ 40, 60, 70, 80 }" + register "fans[1].curve.speed" = "{ 16, 25, 50, 100 }" + end + end + device ref hda on + subsystemid 0x1558 0x4019 + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + end +end + diff --git a/src/mainboard/clevo/tgl-u/vboot-rwa.fmd b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd new file mode 100644 index 0000000..5385db3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + RW_MISC 400K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + } + + RW_SECTION_A { + VBLOCK_A 0x2000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + CONSOLE 0x20000 + + # align this with a WP region? + WP_RO 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: payloads/tianocore: Allow custom build parameters for custom builds
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Martin Roth, Michał Żygowski, Stefan Reinauer. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62497 to review the following change. Change subject: payloads/tianocore: Allow custom build parameters for custom builds ...................................................................... payloads/tianocore: Allow custom build parameters for custom builds Currently custom TianoCore builds are allowed, but those may need different parameters. Add na Kconfig option to specify additional parameters to be appended to build comamnd. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/62497/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5c15af5..42a4585 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -144,6 +144,7 @@ CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \ CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ + CONFIG_TIANOCORE_CUSTOM=$(CONFIG_TIANOCORE_CUSTOM) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \ @@ -153,6 +154,7 @@ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ + CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS=$(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 2ef77ba..90e2fdc 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -146,4 +146,15 @@ endif +if TIANOCORE_CUSTOM + +config TIANOCORE_CUSTOM_BUILD_PARAMS + string "TianoCore custom build parameters" + help + Custom TianoCore forks may have different sets of parameters passed + to build command. You may specify additional parameters to the custom + TianoCore build + +endif + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 6dbfe72..3fe5e27 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -54,6 +54,12 @@ bootloader = $(word 8,$(subst /, ,$(BUILD_STR))) +ifeq ($(CONFIG_TIANOCORE_CUSTOM),y) +ifneq ($(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS),) +BUILD_STR += $(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) +endif +endif + export EDK_TOOLS_PATH=$(project_dir)/BaseTools all: clean build @@ -96,6 +102,7 @@ build: update checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1 echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)" + echo " build $(BUILD_STR)" if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ -- To view, visit https://review.coreboot.org/c/coreboot/+/62497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 Gerrit-Change-Number: 62497 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 Driver provides the Nvidia switchable graphics functionality. Supports S0ix and switching the graphics to on and off state. TEST=Test the Nvidia graphics on Clevo NV41 under Windows with Nvidia drivers. Check the power consumption on Linux when manually toggling _ON and _OFF methods with acpi_exec and draw sample shapes in 3D with dGPU. Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 --- A src/drivers/gfx/nvidia/optimus/Kconfig A src/drivers/gfx/nvidia/optimus/Makefile.inc A src/drivers/gfx/nvidia/optimus/chip.h A src/drivers/gfx/nvidia/optimus/optimus.c 4 files changed, 447 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/62496/1 diff --git a/src/drivers/gfx/nvidia/optimus/Kconfig b/src/drivers/gfx/nvidia/optimus/Kconfig new file mode 100644 index 0000000..e93d836 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Kconfig @@ -0,0 +1,7 @@ +config DRIVER_NVIDIA_OPTIMUS + bool + default n + depends on HAVE_ACPI_TABLES && PMC_IPC_ACPI_INTERFACE + help + NVIDIA Optimus driver for ULT platforms with a PMC IPC ACPI interface. + and graphics cards supporting Runtime D3 power management diff --git a/src/drivers/gfx/nvidia/optimus/Makefile.inc b/src/drivers/gfx/nvidia/optimus/Makefile.inc new file mode 100644 index 0000000..bd60c82 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVER_NVIDIA_OPTIMUS) += optimus.c diff --git a/src/drivers/gfx/nvidia/optimus/chip.h b/src/drivers/gfx/nvidia/optimus/chip.h new file mode 100644 index 0000000..b0eb4c6 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/chip.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ +#define __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ + +#include <acpi/acpi_device.h> + +/* Device support at least one of enable/reset GPIO. */ +struct drivers_gfx_nvidia_optimus_config { + const char *desc; + + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + + /* + * SRCCLK assigned to this root port which will be turned off via PMC IPC. + * If set to -1 then the clock will not be disabled in D3. + */ + int srcclk_pin; + + /* + * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. + * maybe unneeded for optimus? + */ + bool disable_l23; + + /* + * EC method to call on dGPU power state change + */ + const char *ec_notify_method; +}; + +#endif diff --git a/src/drivers/gfx/nvidia/optimus/optimus.c b/src/drivers/gfx/nvidia/optimus/optimus.c new file mode 100644 index 0000000..8b7474c --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/optimus.c @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci.h> +#include <intelblocks/pmc.h> +#include <intelblocks/pmc_ipc.h> +#include <intelblocks/pcie_rp.h> +#include <soc/iomap.h> +#include "chip.h" + +/* PCIe Root Port registers for link status and L23 control. */ +#define PCH_PCIE_CFG_SSID 0x40 /* Subsystem ID */ +#define PCH_PCIE_CFG_LSTS 0x52 /* Link Status Register */ +#define PCH_PCIE_CFG_SPR 0xe0 /* Scratchpad */ +#define PCH_PCIE_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ +#define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ + +/* ACPI register names corresponding to PCIe root port registers. */ +#define ACPI_REG_PCI_LINK_ACTIVE "LASX" /* Link active status */ +#define ACPI_REG_PCI_L23_RDY_ENTRY "L23E" /* L23_Rdy Entry Request */ +#define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ +#define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ + +/* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ +#define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" + +/* ACPI register names corresponding to GPU port registers */ +#define ACPI_REG_PCI_SUBSYSTEM_ID "DVID" /* Subsystem DID+VID */ + +enum modphy_pg_state { + PG_DISABLE = 0, + PG_ENABLE = 1, +}; + +/* Called from _ON to get PCIe link back to active state. */ +static void pcie_rtd3_acpi_l23_exit(void) +{ + /* Skip if port is not in L2/L3. */ + acpigen_write_if_lequal_namestr_int(ACPI_REG_PCI_L23_SAVE_STATE, 1); + + /* Initiate L2/L3 Ready To Detect transition. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_DETECT); + + /* Wait for transition to detect. */ + acpigen_write_delay_until_namestr_int(320, ACPI_REG_PCI_L23_RDY_DETECT, 0); + + acpigen_write_store_int_to_namestr(0, ACPI_REG_PCI_L23_SAVE_STATE); + + /* Once in detect, wait for link active. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_LINK_ACTIVE, 1); + + acpigen_pop_len(); /* If */ +} + +/* Called from _OFF to put PCIe link into L2/L3 state. */ +static void pcie_rtd3_acpi_l23_entry(void) +{ + /* Initiate L2/L3 Entry request. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_ENTRY); + + /* Wait for L2/L3 Entry request to clear. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_L23_RDY_ENTRY, 0); + + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); +} + +/* Called from _ON/_OFF to disable/enable ModPHY power gating */ +static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp, enum modphy_pg_state state) +{ + /* Enter the critical section */ + acpigen_emit_ext_op(ACQUIRE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); + acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); + + acpigen_write_store_int_to_namestr(state, "EMPG"); + acpigen_write_delay_until_namestr_int(100, "AMPG", state); + + /* Exit the critical section */ + acpigen_emit_ext_op(RELEASE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); +} + +/* Restore the subsystem ID after _ON to ensure the windows driver works */ +static void nvidia_optimus_acpi_subsystem_id_restore(const struct device *dev) +{ + uint32_t did, vid, dvid; + + if (CONFIG_SUBSYSTEM_VENDOR_ID) + vid = CONFIG_SUBSYSTEM_VENDOR_ID; + else if (dev->subsystem_vendor) + vid = dev->subsystem_vendor; + else + vid = 0x0000; + + if (CONFIG_SUBSYSTEM_DEVICE_ID) + did = CONFIG_SUBSYSTEM_DEVICE_ID; + else if (dev->subsystem_device) + did = dev->subsystem_device; + else + did = 0x0000; + + dvid = did << 16 | vid; + acpigen_write_store_int_to_namestr(dvid, ACPI_REG_PCI_SUBSYSTEM_ID); +} + +static void +nvidia_optimus_acpi_method_on(unsigned int pcie_rp, + const struct device *dev, + enum pcie_rp_type rp_type) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_ON", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0x5); + + /* Disable modPHY power gating for PCH RPs. */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + + + /* Assert enable GPIO to turn on device power. */ + if (config->enable_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->enable_gpio); + if (config->enable_delay_ms) + acpigen_write_sleep(config->enable_delay_ms); + } + + /* Enable SRCCLK for root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + + /* De-assert reset GPIO to bring device out of reset. */ + if (config->reset_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->reset_gpio); + if (config->reset_delay_ms) + acpigen_write_sleep(config->reset_delay_ms); + } + + /* Trigger L23 ready exit flow unless disabled by config. */ + if (!config->disable_l23) + pcie_rtd3_acpi_l23_exit(); + + /* Notify EC to start polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(1); + } + + nvidia_optimus_acpi_subsystem_id_restore(dev); + acpigen_write_store_int_to_namestr(0xF, "_STA"); + + acpigen_pop_len(); /* If */ + acpigen_pop_len(); /* Method */ +} + +static void +nvidia_optimus_acpi_method_off(unsigned int pcie_rp, + const struct device *dev, + enum pcie_rp_type rp_type) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0xF); + + /* Notify EC to stop polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(0); + } + + /* Trigger L23 ready entry flow unless disabled by config. */ + if (!config->disable_l23) + pcie_rtd3_acpi_l23_entry(); + + /* Assert reset GPIO to place device into reset. */ + if (config->reset_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->reset_gpio); + if (config->reset_off_delay_ms) + acpigen_write_sleep(config->reset_off_delay_ms); + } + + /* Enable modPHY power gating for PCH RPs */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_ENABLE); + + /* Disable SRCCLK for this root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + + /* De-assert enable GPIO to turn off device power. */ + if (config->enable_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->enable_gpio); + if (config->enable_off_delay_ms) + acpigen_write_sleep(config->enable_off_delay_ms); + } + + acpigen_pop_len(); /* If */ + + acpigen_write_store_int_to_namestr(0x5, "_STA"); + acpigen_pop_len(); /* Method */ +} + +static int get_pcie_rp_pmc_idx(enum pcie_rp_type rp_type, const struct device *dev) +{ + int idx = -1; + + switch (rp_type) { + case PCIE_RP_PCH: + /* Read port number of root port that this device is attached to. */ + idx = pci_read_config8(dev, PCH_PCIE_CFG_LCAP_PN); + + /* Port number is 1-based, PMC IPC method expects 0-based. */ + idx--; + break; + case PCIE_RP_CPU: + /* CPU RPs are indexed by their "virtual wire index" to the PCH */ + idx = soc_get_cpu_rp_vw_idx(dev); + break; + default: + break; + } + + return idx; +} + +static void write_modphy_opregion(unsigned int pcie_rp) +{ + /* The register containing the Power Gate enable sequence bits is at + PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at + PCH_PWRM_BASE + 0x10D4. */ + const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(0xD0), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ + FIELDLIST_OFFSET(0xD4), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ + }; + + acpigen_write_opregion(&opregion); + acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +} + +static void nvidia_optimus_acpi_fill_ssdt(const struct device *dev) +{ + static bool mutex_created = false; + + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + static const char *const power_res_states[] = {"_PR0", "_PR2", "_PR3"}; + const struct device *parent = dev->bus->dev; + const char *scope = acpi_device_path(parent); + + /* PCH RP PCIe configuration space */ + const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); + const struct fieldlist rp_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), + FIELDLIST_RESERVED(13), + FIELDLIST_NAMESTR(ACPI_REG_PCI_LINK_ACTIVE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_SPR), + FIELDLIST_RESERVED(7), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_SAVE_STATE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_RPPGEN), + FIELDLIST_RESERVED(2), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), + }; + int pcie_rp; + + /* dGPU PCIe configuration space */ + const struct opregion gpu_pci_config = OPREGION("PCIC", PCI_CONFIG, 0, 0x50); + const struct fieldlist gpu_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_SSID), + FIELDLIST_NAMESTR(ACPI_REG_PCI_SUBSYSTEM_ID, 32), + }; + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->enable_gpio.pin_count && !config->reset_gpio.pin_count) { + printk(BIOS_ERR, "%s: Enable and/or Reset GPIO required for %s.\n", + __func__, scope); + return; + } + if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { + printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, + config->srcclk_pin, scope); + return; + } + + const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); + pcie_rp = get_pcie_rp_pmc_idx(rp_type, parent); + if (pcie_rp < 0) { + printk(BIOS_ERR, "%s: Unknown PCIe root port\n", __func__); + return; + } + + printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + + /* Create a mutex for exclusive access to the PMC registers. */ + if (rp_type == PCIE_RP_PCH && !mutex_created) { + acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_mutex("R3MX", 0); + acpigen_write_scope_end(); + mutex_created = true; + } + + /* The RTD3 power resource is added to the root port, not the device. */ + acpigen_write_scope(scope); + + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 1); + + acpigen_write_method_serialized("_ON", 0); + acpigen_write_store_int_to_namestr(1, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_store_int_to_namestr(0, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_pop_len(); /* PowerResource */ + + /* GPU scope */ + acpigen_write_device("DEV0"); + acpigen_write_name_integer("_ADR", 0x0); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + + acpigen_write_opregion(&rp_pci_config); + acpigen_write_field("PXCS", rp_fieldlist, ARRAY_SIZE(rp_fieldlist), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_opregion(&gpu_pci_config); + acpigen_write_field("PCIC", gpu_fieldlist, ARRAY_SIZE(gpu_fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ + if (rp_type == PCIE_RP_PCH) + write_modphy_opregion(pcie_rp); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 0xF); + + /* + * The ON and OFF methods must be in dGPU scope, otherwise the dGPU is + * not properly switched. + */ + nvidia_optimus_acpi_method_on(pcie_rp, dev, rp_type); + nvidia_optimus_acpi_method_off(pcie_rp, dev, rp_type); + + acpigen_pop_len(); /* PowerResource */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *nvidia_optimus_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static struct device_operations nvidia_optimus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = nvidia_optimus_acpi_fill_ssdt, + .acpi_name = nvidia_optimus_acpi_name, + .ops_pci = &pci_dev_ops_pci, +}; + +static void nvidia_optimus_acpi_enable(struct device *dev) +{ + dev->ops = &nvidia_optimus_ops; +} + +struct chip_operations drivers_gfx_nvidia_optimus_ops = { + CHIP_NAME("NVIDIA Optimus Hybrid Graphics") + .enable_dev = nvidia_optimus_acpi_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Michał Żygowski. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62495 to review the following change. Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops ...................................................................... ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops This is IT5570 EC implementation for Clevo laptops with Insyde firmware. The driver and ACPI code support all functionalities, including dGPU, FN keys, Type-C UCSI and S0ix. The only issue is with TP toggle hotkey when TP works in I2C HID mode under Linux. One needs to add udev rules as specified in: https://docs.dasharo.com/variants/clevo_nv41/post_install/ Windows can handle the EC query function that toggles the TP's _STA field and OS disables/enabels the touchpad accordingly. TEST=Boot Ubuntu and Windows 11 on Clevo NV41 and see battery/AC is detected, S0ix is working and FN keys are functional. Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I07c7d1d4f86d764bd10cfa3b0da23d1116281f3b --- A src/ec/clevo/it5570/Kconfig A src/ec/clevo/it5570/Makefile.inc A src/ec/clevo/it5570/acpi/ac.asl A src/ec/clevo/it5570/acpi/battery.asl A src/ec/clevo/it5570/acpi/buttons.asl A src/ec/clevo/it5570/acpi/ec.asl A src/ec/clevo/it5570/acpi/ec_ram.asl A src/ec/clevo/it5570/acpi/gpe.asl A src/ec/clevo/it5570/acpi/hid.asl A src/ec/clevo/it5570/acpi/lid.asl A src/ec/clevo/it5570/acpi/ucsi.asl A src/ec/clevo/it5570/chip.c A src/ec/clevo/it5570/chip.h A src/ec/clevo/it5570/ec.c A src/ec/clevo/it5570/ec.h 15 files changed, 1,666 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/62495/1 diff --git a/src/ec/clevo/it5570/Kconfig b/src/ec/clevo/it5570/Kconfig new file mode 100644 index 0000000..bdd3a59 --- /dev/null +++ b/src/ec/clevo/it5570/Kconfig @@ -0,0 +1,14 @@ +config EC_CLEVO_IT5570 + bool + select EC_ACPI + help + Clevo IT5570 EC + +config EC_CLEVO_IT5570_RAM_BASE + depends on EC_CLEVO_IT5570 + hex + default 0xfe0b0100 + help + The base of LPC window that maps the EC RAM to host memory space. + This is the ACPI address for EC RAM, the address programmed to registers + is always rounded to the nearest 64K. diff --git a/src/ec/clevo/it5570/Makefile.inc b/src/ec/clevo/it5570/Makefile.inc new file mode 100644 index 0000000..1568d94 --- /dev/null +++ b/src/ec/clevo/it5570/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_EC_CLEVO_IT5570),y) + +ramstage-y += chip.c +ramstage-y += ec.c + +smm-y += ec.c + +endif diff --git a/src/ec/clevo/it5570/acpi/ac.asl b/src/ec/clevo/it5570/acpi/ac.asl new file mode 100644 index 0000000..7326676 --- /dev/null +++ b/src/ec/clevo/it5570/acpi/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/ec/clevo/it5570/acpi/battery.asl b/src/ec/clevo/it5570/acpi/battery.asl new file mode 100644 index 0000000..bc239dd --- /dev/null +++ b/src/ec/clevo/it5570/acpi/battery.asl @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/ec/clevo/it5570/acpi/buttons.asl b/src/ec/clevo/it5570/acpi/buttons.asl new file mode 100644 index 0000000..040d189 --- /dev/null +++ b/src/ec/clevo/it5570/acpi/buttons.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { EC_GPE_PWRB, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { EC_GPE_SLPB, 3 }) +} diff --git a/src/ec/clevo/it5570/acpi/ec.asl b/src/ec/clevo/it5570/acpi/ec.asl new file mode 100644 index 0000000..f894a0f --- /dev/null +++ b/src/ec/clevo/it5570/acpi/ec.asl @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Generated in SSDT */ +External (\_SB.PCI0.LPCB.EC0.SFCV, MethodObj) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x002e, // Range Minimum + 0x002e, // Range Maximum + 0x00, // Alignment + 0x02, // Length + ) + }) + + #include "ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + If (((Arg0 == 0x03) && (Arg1 == One))) { + // Enable hardware touchpad lock and keyboard backlight keys + // Enable software airplane mode key + ECOS = 2 + + // Enable software display brightness keys + WINF = 1 + + // Enable camera toggle hotkey + OEM3 = OEM3 | 4 + + // Set current AC state + \_SB.AC.ACFG = ADP + // Update battery information and status + \_SB.BAT0.UPBI () + \_SB.BAT0.UPBS () + + PNOT () + + // Initialize UCSI + ^UCSI.INIT () + + // Apply custom fan curve + \_SB.PCI0.LPCB.EC0.SFCV () + + // EC is now available + ECOK = Arg1 + } + } + + Method (UPB, 0, Serialized) { + Debug = "EC: UPB" + // Set current AC state + \_SB.AC.ACFG = ADP + + // Update battery information and status + \_SB.BAT0.UPBI () + \_SB.BAT0.UPBS () + + // Notify of changes + Notify(\_SB.AC, Zero) + Notify(\_SB.BAT0, Zero) + + Sleep (1000) + } + + Method (PTS, 1, Serialized) { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + // Clear wake cause + WFNO = Zero + } + } + + Method (WAK, 1, Serialized) { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + UPB () + \_SB.PCI0.LPCB.EC0.SFCV () + } + } + + Method (I2ER, 1, NotSerialized) + { + SIOI = 0x2e + SIOD = 0x11 + SIOI = 0x2f + SIOD = ((Arg0 >> 8) & 0xff) + SIOI = 0x2e + SIOD = 0x10 + SIOI = 0x2f + SIOD = (Arg0 & 0xff) + SIOI = 0x2e + SIOD = 0x12 + SIOI = 0x2f + Local0 = SIOD + + Return (Local0) + } + + Method (I2EW, 2, NotSerialized) + { + SIOI = 0x2e + SIOD = 0x11 + SIOI = 0x2f + SIOD = ((Arg0 >> 8) & 0xff) + SIOI = 0x2e + SIOD = 0x10 + SIOI = 0x2f + SIOD = (Arg0 & 0xff) + SIOI = 0x2e + SIOD = 0x12 + SIOI = 0x2f + + SIOD = Arg1; + } + + Method (GKBL, 0, Serialized) // Get Keyboard LED + { + Local0 = 0 + If (ECOK) { + FDAT = One + FCMD = 0xCA + Local0 = FBUF + FCMD = Zero + } + Return (Local0) + } + + Method (SKBL, 1, Serialized) // Set Keyboard LED + { + If (ECOK) { + FDAT = Zero + FBUF = Arg0 + FCMD = 0xCA + } + } + + Method (S0IX, 1, Serialized) // S0IX Entry/Exit + { + If (Arg0) { + Debug = "EC: S0IX Enter" + } Else { + Debug = "EC: S0IX Exit" + UPB () + \_SB.PCI0.LPCB.EC0.SFCV () + } + + FDAT = 0xC2 + FBUF = Arg0 + FCMD = 0xD2 + Local0 = 0xFF + Local1 = 0xFF + While (Local0 != Arg0 && Local1 > Zero) + { + Sleep(50) + FDAT = 0xC3 + FCMD = 0xD2 + Local3 = FBUF + If (Local3 == Zero || Local3 == One) + { + Local0 = Local3 + } + Local1 = Local1 - 1 + } + } + + Method (DGPM, 1, Serialized) // Handle dGPU power state change + { + If (ECOK) { + If (Arg0 == 0x0) { + AIRP &= 0x7F + Debug = "EC: DGPU Off" + } ElseIf (Arg0 == 0x1) { + AIRP |= 0x80 + Debug = "EC: DGPU On" + } + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Debug = "EC: Touchpad Toggle" + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Debug = "EC: Screen Toggle" + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Debug = "EC: Mute" + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Debug = "EC: Keyboard Backlight" + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Debug = "EC: Volume Down" + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Debug = "EC: Volume Up" + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Debug = "EC: Switch Video Mode" + If (CondRefOf (\_SB.PCI0.GFX0)) { + Notify (\_SB.PCI0.GFX0, 0x80) + } + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Debug = "EC: Brightness Down" + + If (CondRefOf (\_SB.PCI0.GFX0.LCD0)) { + Notify (\_SB.PCI0.GFX0.LCD0, 0x87) + } + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Debug = "EC: Brightness Up" + + If (CondRefOf (\_SB.PCI0.GFX0.LCD0)) { + Notify (\_SB.PCI0.GFX0.LCD0, 0x86) + } + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Debug = "EC: Camera Toggle" + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Debug = "EC: Airplane Mode" + + If (CondRefOf (^HIDD.HPEM)) + { + ^HIDD.HPEM (8) + } + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Debug = "EC: Suspend Button" + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Debug = "EC: AC Detect" + + If (MSFG) + { + FDAT = Zero + FBUF = 0xC1 + FCMD = 0xD2 + If ((FBUF & 0x80)) + { + FBUF = Zero + Return (Zero) + } + } + + \_SB.AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (\_SB.BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (\_SB.BAT0, 0x80) // Status Change + Sleep (0x32) + } + + Return (Zero) + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (17)" + Notify (\_SB.BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (19)" + Notify (\_SB.BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Debug = "EC: Lid Close" + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Debug = "EC: Thermal Trip" + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Debug = "EC: Power Button" + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Debug = "EC: White Keyboard Backlight" + } ElseIf (Local0 == 0x9F) { + Debug = "EC: Color Keyboard Toggle" + } ElseIf (Local0 == 0x81) { + Debug = "EC: Color Keyboard Down" + } ElseIf (Local0 == 0x82) { + Debug = "EC: Color Keyboard Up" + } ElseIf (Local0 == 0x80) { + Debug = "EC: Color Keyboard Color Change" + } ElseIf (Local0 == 0xF3) { + Debug = "EC: Fan Cooling Mode Enable" + } ElseIf (Local0 == 0x6C) { + Debug = "EC: Fan Cooling Mode Disable" + \_SB.PCI0.LPCB.EC0.SFCV () + } Else { + Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + } + } + + Method (_Q62, 0, NotSerialized) // UCSI event + { + Debug = "EC: UCSI Event" + ^UCSI.MGI0 = MGI0 + ^UCSI.MGI1 = MGI1 + ^UCSI.MGI2 = MGI2 + ^UCSI.MGI3 = MGI3 + ^UCSI.MGI4 = MGI4 + ^UCSI.MGI5 = MGI5 + ^UCSI.MGI6 = MGI6 + ^UCSI.MGI7 = MGI7 + ^UCSI.MGI8 = MGI8 + ^UCSI.MGI9 = MGI9 + ^UCSI.MGIA = MGIA + ^UCSI.MGIB = MGIB + ^UCSI.MGIC = MGIC + ^UCSI.MGID = MGID + ^UCSI.MGIE = MGIE + ^UCSI.MGIF = MGIF + ^UCSI.CCI0 = CCI0 + ^UCSI.CCI1 = CCI1 + ^UCSI.CCI2 = CCI2 + ^UCSI.CCI3 = CCI3 + Notify (^UCSI, 0x80) + } + + #include "hid.asl" + #include "ucsi.asl" +} diff --git a/src/ec/clevo/it5570/acpi/ec_ram.asl b/src/ec/clevo/it5570/acpi/ec_ram.asl new file mode 100644 index 0000000..ce8cce0 --- /dev/null +++ b/src/ec/clevo/it5570/acpi/ec_ram.asl @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ERAM, SystemMemory, CONFIG_EC_CLEVO_IT5570_RAM_BASE, 0x400) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + DPTT, 8, + DPT1, 8, + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + OEM5, 8, + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + FN_G, 1, + Offset (0xE5), + INF3, 8, + DFAL, 1, + DFAE, 1, + Offset (0xE7), + XFAN, 8, + , 2, + MAXQ, 1, + Offset (0xE9), + EKBS, 1, + Offset (0xEA), + , 4, + MSFG, 1, + RCHG, 1, + ACOT, 1, + S5FG, 1, + , 3, + DGPT, 1, + TOPN, 1, + , 1, + APRD, 1, + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0x280), + KLCR, 8, + KLCG, 8, + KLCB, 8, + KMCR, 8, + KMCG, 8, + KMCB, 8, + KRCR, 8, + KRCG, 8, + KRCB, 8, + KBNS, 8, + FANC, 8, + KBLD, 8, + P1F1, 8, + P2F1, 8, + P3F1, 8, + P4F1, 8, + P1D1, 8, + P2D1, 8, + P3D1, 8, + P4D1, 8, + SH11, 8, + SL11, 8, + SH12, 8, + SL12, 8, + SH13, 8, + SL13, 8, + P1F2, 8, + P2F2, 8, + P3F2, 8, + P4F2, 8, + P1D2, 8, + P2D2, 8, + P3D2, 8, + P4D2, 8, + SH21, 8, + SL21, 8, + SH22, 8, + SL22, 8, + SH23, 8, + SL23, 8, + P1F3, 8, + P2F3, 8, + P3F3, 8, + P4F3, 8, + P1D3, 8, + P2D3, 8, + P3D3, 8, + P4D3, 8, + SH31, 8, + SL31, 8, + SH32, 8, + SL32, 8, + SH33, 8, + SL33, 8, + Offset (0x2CF), + VER0, 8, + VER1, 8, + RSV1, 8, + RSV2, 8, + CCI0, 8, + CCI1, 8, + CCI2, 8, + CCI3, 8, + CTL0, 8, + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + MGI0, 8, + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + MGO0, 8, + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + MSTS, 8 +} + +OperationRegion (EC81, EmbeddedControl, Zero, 0xFF) +Field (EC81, ByteAcc, Lock, Preserve) +{ + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} + +OperationRegion (SIO, SystemIO, 0x2e, 0x02) +Field (SIO, ByteAcc, Lock, Preserve) +{ + SIOI, 8, + SIOD, 8 +} diff --git a/src/ec/clevo/it5570/acpi/gpe.asl b/src/ec/clevo/it5570/acpi/gpe.asl new file mode 100644 index 0000000..68f33a6 --- /dev/null +++ b/src/ec/clevo/it5570/acpi/gpe.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_L02, 0, Serialized) { + Debug = Concatenate("GPE_L02: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/ec/clevo/it5570/acpi/hid.asl b/src/ec/clevo/it5570/acpi/hid.asl new file mode 100644 index 0000000..5c7d448 --- /dev/null +++ b/src/ec/clevo/it5570/acpi/hid.asl @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Device (HIDD) +{ + Name (_HID, "INTC1051") // _HID: Hardware ID + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HMDE, Zero) + Name (HRDY, Zero) + Name (BTLD, Zero) + Name (BTS1, Zero) + Name (HEB1, 0x02) + Name (HEB2, Zero) + Name (BIST, Zero) + + Name (DPKG, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + + Method (_STA, 0, Serialized) // _STA: Status + { + Return (0x0F) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("eeec56b3-4442-408f-a792-4edd4d758054"))) + { + If ((One == ToInteger (Arg1))) + { + BIST = One + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 + }) + } + Case (One) + { + BTNL () + } + Case (0x02) + { + Return (HDMM ()) + } + Case (0x03) + { + HDSM (DerefOf (Arg3 [Zero])) + } + Case (0x04) + { + Return (HDEM ()) + } + Case (0x05) + { + Return (BTNS ()) + } + Case (0x06) + { + BTNE (DerefOf (Arg3 [Zero])) + } + Case (0x07) + { + Return (HEBC ()) + } + Case (0x08) + { + } + + } + } + Else + { + BIST = Zero + } + } + + Return (Buffer (One) { 0x00 }) + } + + Method (HDDM, 0, Serialized) + { + Return (DPKG) + } + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + If ((HMDE == Zero)) + { + Return (HIDX) + } + + Return (HMDE) + } + + Method (HDMM, 0, Serialized) + { + Return (HMDE) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + If ((HMDE == Zero)) + { + HIDX = Arg0 + } + Else + { + HIDX = Arg0 + } + + Notify (HIDD, 0xC0) + Local0 = Zero + + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } + + Method (BTNL, 0, Serialized) + { + BTS1 = Zero + } + + Method (BTNE, 1, Serialized) + { + BTS1 = ((Arg0 & 0x1E) | One) + } + + Method (BTNS, 0, Serialized) + { + Return (BTS1) + } + + Method (BTNC, 0, Serialized) + { + Return (Zero) + } + + Method (HEBC, 0, Serialized) + { + Return (HEB1) + } + + Method (HEEC, 0, Serialized) + { + Return (HEB2) + } +} diff --git a/src/ec/clevo/it5570/acpi/lid.asl b/src/ec/clevo/it5570/acpi/lid.asl new file mode 100644 index 0000000..5f7ca6d --- /dev/null +++ b/src/ec/clevo/it5570/acpi/lid.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { EC_GPE_LID, 3 }) + + Method (_LID, 0, NotSerialized) { + DEBUG = "LID: _LID" + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) { + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/ec/clevo/it5570/acpi/ucsi.asl b/src/ec/clevo/it5570/acpi/ucsi.asl new file mode 100644 index 0000000..ad8450a --- /dev/null +++ b/src/ec/clevo/it5570/acpi/ucsi.asl @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (UCSI) +{ + Name (_HID, EisaId ("USBC000")) + Name (_CID, EisaId ("PNP0CA0")) + Name (_UID, One) + Name (_DDN, "USB Type-C") + Name (_STA, 0xf) + + /* Shared memory fields are defined in the SSDT */ + External (\_SB.PCI0.LPCB.EC0.UCSI.VER0, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.VER1, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CCI0, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CCI1, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CCI2, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CCI3, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL0, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL1, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL2, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL3, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL4, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL5, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL6, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.CTL7, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI0, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI1, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI2, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI3, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI4, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI5, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI6, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI7, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI8, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGI9, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGIA, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGIB, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGIC, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGID, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGIE, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGIF, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO0, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO1, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO2, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO3, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO4, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO5, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO6, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO7, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO8, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGO9, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOA, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOB, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOC, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOD, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOE, FieldUnitObj) + External (\_SB.PCI0.LPCB.EC0.UCSI.MGOF, FieldUnitObj) + + Method (INIT) + { + /* Read UCSI version from EC into shared memory */ + VER0 = \_SB.PCI0.LPCB.EC0.VER0 + VER1 = \_SB.PCI0.LPCB.EC0.VER1 + } + + Method (_DSM, 4, Serialized) + { + If (Arg0 != ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f")) { + Return (Buffer (One) { Zero }) + } + + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) { 0x0F }) + } + Case (One) + { + /* Write Message Out */ + \_SB.PCI0.LPCB.EC0.MGO0 = MGO0 + \_SB.PCI0.LPCB.EC0.MGO1 = MGO1 + \_SB.PCI0.LPCB.EC0.MGO2 = MGO2 + \_SB.PCI0.LPCB.EC0.MGO3 = MGO3 + \_SB.PCI0.LPCB.EC0.MGO4 = MGO4 + \_SB.PCI0.LPCB.EC0.MGO5 = MGO5 + \_SB.PCI0.LPCB.EC0.MGO6 = MGO6 + \_SB.PCI0.LPCB.EC0.MGO7 = MGO7 + \_SB.PCI0.LPCB.EC0.MGO8 = MGO8 + \_SB.PCI0.LPCB.EC0.MGO9 = MGO9 + \_SB.PCI0.LPCB.EC0.MGOA = MGOA + \_SB.PCI0.LPCB.EC0.MGOB = MGOB + \_SB.PCI0.LPCB.EC0.MGOC = MGOC + \_SB.PCI0.LPCB.EC0.MGOD = MGOD + \_SB.PCI0.LPCB.EC0.MGOE = MGOE + \_SB.PCI0.LPCB.EC0.MGOF = MGOF + + /* Write Control */ + \_SB.PCI0.LPCB.EC0.CTL0 = CTL0 + \_SB.PCI0.LPCB.EC0.CTL1 = CTL1 + \_SB.PCI0.LPCB.EC0.CTL2 = CTL2 + \_SB.PCI0.LPCB.EC0.CTL3 = CTL3 + \_SB.PCI0.LPCB.EC0.CTL4 = CTL4 + \_SB.PCI0.LPCB.EC0.CTL5 = CTL5 + \_SB.PCI0.LPCB.EC0.CTL6 = CTL6 + \_SB.PCI0.LPCB.EC0.CTL7 = CTL7 + + /* Start EC Command */ + \_SB.PCI0.LPCB.EC0.FDAT = One + \_SB.PCI0.LPCB.EC0.FCMD = 0xE0 + } + Case (2) + { + /* Read Message In */ + MGI0 = \_SB.PCI0.LPCB.EC0.MGI0 + MGI1 = \_SB.PCI0.LPCB.EC0.MGI1 + MGI2 = \_SB.PCI0.LPCB.EC0.MGI2 + MGI3 = \_SB.PCI0.LPCB.EC0.MGI3 + MGI4 = \_SB.PCI0.LPCB.EC0.MGI4 + MGI5 = \_SB.PCI0.LPCB.EC0.MGI5 + MGI6 = \_SB.PCI0.LPCB.EC0.MGI6 + MGI7 = \_SB.PCI0.LPCB.EC0.MGI7 + MGI8 = \_SB.PCI0.LPCB.EC0.MGI8 + MGI9 = \_SB.PCI0.LPCB.EC0.MGI9 + MGIA = \_SB.PCI0.LPCB.EC0.MGIA + MGIB = \_SB.PCI0.LPCB.EC0.MGIB + MGIC = \_SB.PCI0.LPCB.EC0.MGIC + MGID = \_SB.PCI0.LPCB.EC0.MGID + MGIE = \_SB.PCI0.LPCB.EC0.MGIE + MGIF = \_SB.PCI0.LPCB.EC0.MGIF + + /* Read Status */ + CCI0 = \_SB.PCI0.LPCB.EC0.CCI0 + CCI1 = \_SB.PCI0.LPCB.EC0.CCI1 + CCI2 = \_SB.PCI0.LPCB.EC0.CCI2 + CCI3 = \_SB.PCI0.LPCB.EC0.CCI3 + } + } + Return (Buffer (One) { Zero }) + } +} diff --git a/src/ec/clevo/it5570/chip.c b/src/ec/clevo/it5570/chip.c new file mode 100644 index 0000000..a16266d --- /dev/null +++ b/src/ec/clevo/it5570/chip.c @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/bsd/helpers.h> +#include <console/console.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <stdint.h> +#include <stdio.h> +#include "chip.h" + +#define I2EC_ADDR_L 0x10 +#define I2EC_ADDR_H 0x11 +#define I2EC_DATA 0x12 + +#define IT5570_SMFI_LDN 0xf + +#define IT5570_SMFI_LPCMWBA 0xf0 /* LPC Memory Window Base Address */ +#define IT5570_SMFI_HLPCRAMBA 0xf5 /* H2RAM-HLPC Base Address */ +#define IT5570_SMFI_HLPCRAMBA_24 0xfc /* H2RAM-HLPC Base Address */ + +#define IT5570_SMFI_HRAMWC 0x105a /* Host RAM Window Control */ +#define IT5570_SMFI_HRAMW0AAS 0x105d /* Host RAM Window 0 Access Allow Size */ + +enum { + H2RAM_WINDOW_16B, + H2RAM_WINDOW_32B, + H2RAM_WINDOW_64B, + H2RAM_WINDOW_128B, + H2RAM_WINDOW_256B, + H2RAM_WINDOW_512B, + H2RAM_WINDOW_1024B, + H2RAM_WINDOW_2048B, +}; + +/* + * Setting minimum length of UCSI_ACPI will ensure this region is placed out of IMD Small. + * Having this region out of IMD Small will prevent any memory mapping conflicts. + */ +#define UCSI_MIN_ALLOC_REGION_LEN CBMEM_SM_ROOT_SIZE +/* + * The UCSI fields are defined in the UCSI specification at + * https://www.intel.com/content/www/us/en/io/universal-serial-bus/usb-type-c-… + * https://www.intel.com/content/www/us/en/io/universal-serial-bus/bios-implem… + */ + +static struct fieldlist ucsi_region_fields[] = { + FIELDLIST_NAMESTR("VER0", 8), + FIELDLIST_NAMESTR("VER1", 8), + FIELDLIST_NAMESTR("RSV0", 8), + FIELDLIST_NAMESTR("RSV1", 8), + FIELDLIST_NAMESTR("CCI0", 8), + FIELDLIST_NAMESTR("CCI1", 8), + FIELDLIST_NAMESTR("CCI2", 8), + FIELDLIST_NAMESTR("CCI3", 8), + FIELDLIST_NAMESTR("CTL0", 8), + FIELDLIST_NAMESTR("CTL1", 8), + FIELDLIST_NAMESTR("CTL2", 8), + FIELDLIST_NAMESTR("CTL3", 8), + FIELDLIST_NAMESTR("CTL4", 8), + FIELDLIST_NAMESTR("CTL5", 8), + FIELDLIST_NAMESTR("CTL6", 8), + FIELDLIST_NAMESTR("CTL7", 8), + FIELDLIST_NAMESTR("MGI0", 8), + FIELDLIST_NAMESTR("MGI1", 8), + FIELDLIST_NAMESTR("MGI2", 8), + FIELDLIST_NAMESTR("MGI3", 8), + FIELDLIST_NAMESTR("MGI4", 8), + FIELDLIST_NAMESTR("MGI5", 8), + FIELDLIST_NAMESTR("MGI6", 8), + FIELDLIST_NAMESTR("MGI7", 8), + FIELDLIST_NAMESTR("MGI8", 8), + FIELDLIST_NAMESTR("MGI9", 8), + FIELDLIST_NAMESTR("MGIA", 8), + FIELDLIST_NAMESTR("MGIB", 8), + FIELDLIST_NAMESTR("MGIC", 8), + FIELDLIST_NAMESTR("MGID", 8), + FIELDLIST_NAMESTR("MGIE", 8), + FIELDLIST_NAMESTR("MGIF", 8), + FIELDLIST_NAMESTR("MGO0", 8), + FIELDLIST_NAMESTR("MGO1", 8), + FIELDLIST_NAMESTR("MGO2", 8), + FIELDLIST_NAMESTR("MGO3", 8), + FIELDLIST_NAMESTR("MGO4", 8), + FIELDLIST_NAMESTR("MGO5", 8), + FIELDLIST_NAMESTR("MGO6", 8), + FIELDLIST_NAMESTR("MGO7", 8), + FIELDLIST_NAMESTR("MGO8", 8), + FIELDLIST_NAMESTR("MGO9", 8), + FIELDLIST_NAMESTR("MGOA", 8), + FIELDLIST_NAMESTR("MGOB", 8), + FIELDLIST_NAMESTR("MGOC", 8), + FIELDLIST_NAMESTR("MGOD", 8), + FIELDLIST_NAMESTR("MGOE", 8), + FIELDLIST_NAMESTR("MGOF", 8), +}; +static const size_t ucsi_region_len = ARRAY_SIZE(ucsi_region_fields); + +/* Depth 2 space is always avaiable, no need for conf mode */ +static void i2ec_depth2_write(uint8_t index, uint8_t data) +{ + outb(0x2e,0x2e); + outb(index, 0x2f); + outb(0x2f, 0x2e); + outb(data, 0x2f); +} + +static uint8_t i2ec_depth2_read(uint8_t index) +{ + outb(0x2e,0x2e); + outb(index, 0x2f); + outb(0x2f, 0x2e); + return inb(0x2f); +} + +static uint8_t i2ec_direct_read(uint16_t addr) +{ + i2ec_depth2_write(I2EC_ADDR_H, addr >> 8); + i2ec_depth2_write(I2EC_ADDR_L, addr & 0xff); + return i2ec_depth2_read(I2EC_DATA); +} + +static void i2ec_direct_write(uint16_t addr, uint8_t data) +{ + + i2ec_depth2_write(I2EC_ADDR_H, addr >> 8); + i2ec_depth2_write(I2EC_ADDR_L, addr & 0xff); + i2ec_depth2_write(I2EC_DATA, data); +} + +static void it5570_set_h2ram_base(struct device *dev, uint32_t addr) +{ + uint8_t *h2ram_base = (uint8_t *)&addr; + + if (h2ram_base[3] != 0xfe && h2ram_base[3] != 0xff) { + printk(BIOS_ERR, "ERROR: Invalid H2RAM memory window base\n"); + return; + } + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* Configure LPC memory window for LGMR */ + pnp_write_config(dev, IT5570_SMFI_LPCMWBA, h2ram_base[3]); + pnp_write_config(dev, IT5570_SMFI_LPCMWBA + 1, h2ram_base[2]); + + /* Configure H2RAM-HLPC base */ + pnp_write_config(dev, IT5570_SMFI_HLPCRAMBA + 1, h2ram_base[2]); + pnp_write_config(dev, IT5570_SMFI_HLPCRAMBA, h2ram_base[1]); + /* H2RAM-HLPC[24] */ + pnp_write_config(dev, IT5570_SMFI_HLPCRAMBA_24, h2ram_base[3] & 1); + + pnp_exit_conf_mode(dev); + + /* Set H2RAM window 0 size to 1K */ + i2ec_direct_write(IT5570_SMFI_HRAMW0AAS, + i2ec_direct_read(IT5570_SMFI_HRAMW0AAS) | H2RAM_WINDOW_1024B); + /* Set H2RAM through LPC Memory cycle, enable window 0 */ + i2ec_direct_write(IT5570_SMFI_HRAMWC, + (i2ec_direct_read(IT5570_SMFI_HRAMWC) & 0xef) | 1); +} + +static bool is_curve_valid(struct ec_clevo_it5570_fan_curve curve) +{ + int i; + + /* + * Fan curve speeds have to be non-decreasing. + * Fan curve temperatures have to be increasing (to avoid division by 0). + * This also covers the case when the curve is all zeroes (i.e. not configured). + */ + + for (i = 1; i < IT5570_FAN_CURVE_LEN; ++i) + if ( curve.speed[i] < curve.speed[i-1] + || curve.temperature[i] <= curve.temperature[i-1]) + return false; + + return true; +} + +static void write_it5570_fan_curve(struct ec_clevo_it5570_fan_curve curve, int fan) +{ + uint16_t ramp; + int j; + char fieldname[5]; + + /* Curve points */ + for (j = 0; j < 4; ++j) { + snprintf(fieldname, 5, "P%dF%d", j+1, fan+1); + acpigen_write_store_int_to_namestr(curve.temperature[j], fieldname); + snprintf(fieldname, 5, "P%dD%d", j+1, fan+1); + acpigen_write_store_int_to_namestr(curve.speed[j] * 255 / 100, fieldname); + } + + /* Ramps */ + for (j = 0; j < 3; ++j) { + snprintf(fieldname, 5, "SH%d%d", fan+1, j+1); + ramp = (float)(curve.speed[j+1] - curve.speed[j]) + / (float)(curve.temperature[j+1] - curve.temperature[j]) + * 2.55 * 16.0; + acpigen_write_store_int_to_namestr(ramp >> 8, fieldname); + snprintf(fieldname, 5, "SL%d%d", fan+1, j+1); + acpigen_write_store_int_to_namestr(ramp & 0xFF, fieldname); + } +} + +static void clevo_it5570_ec_init(struct device *dev) +{ + if (!dev->enabled) + return; + + printk(BIOS_SPEW, "Clevo IT5570 EC init\n"); + + struct device sio_smfi = { + .path.type = DEVICE_PATH_PNP, + .path.pnp.port = 0x2e, + .path.pnp.device = IT5570_SMFI_LDN, + }; + sio_smfi.ops->ops_pnp_mode = &pnp_conf_mode_870155_aa; + + it5570_set_h2ram_base(&sio_smfi, CONFIG_EC_CLEVO_IT5570_RAM_BASE & 0xfffff000); + + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void clevo_it5570_ec_resource(struct device *dev, int index, size_t base, size_t size) +{ + struct resource *res = new_resource(dev, index); + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->base = base; + res->size = size; +} + +static void clevo_it5570_ec_read_resources(struct device *dev) +{ + /* H2RAM resource */ + clevo_it5570_ec_resource(dev, 0, CONFIG_EC_CLEVO_IT5570_RAM_BASE & 0xffff0000, 64*KiB); +} + +static void clevo_it5570_ec_fill_ssdt_generator(const struct device *dev) +{ + const struct ec_clevo_it5570_config *config = config_of(dev); + struct opregion opreg; + void *region_ptr; + size_t ucsi_alloc_region_len; + uint8_t i; + + /* UCSI */ + ucsi_alloc_region_len = ucsi_region_len < UCSI_MIN_ALLOC_REGION_LEN ? + UCSI_MIN_ALLOC_REGION_LEN : ucsi_region_len; + region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_alloc_region_len); + if (!region_ptr) + return; + memset(region_ptr, 0, ucsi_alloc_region_len); + + opreg.name = "UCSM"; + opreg.regionspace = SYSTEMMEMORY; + opreg.regionoffset = (uintptr_t)region_ptr; + opreg.regionlen = ucsi_region_len; + + acpigen_write_scope(acpi_device_path_join(dev, "UCSI")); + acpigen_write_name_integer("_ADR", 0); + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, (uintptr_t)region_ptr, ucsi_region_len); + acpigen_write_resourcetemplate_footer(); + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, ucsi_region_fields, ucsi_region_len, + FIELD_ANYACC | FIELD_LOCK | FIELD_PRESERVE); + acpigen_pop_len(); /* Scope */ + + /* Fan curve */ + /* have the function exist even if the fan curve isn't enabled in devicetree */ + acpigen_write_scope(acpi_device_path(dev)); + acpigen_write_method("SFCV", 0); + if (config->fan_mode == FAN_MODE_CUSTOM) { + if (!is_curve_valid(config->fans[0].curve)) { + printk (BIOS_ERR, "EC: Fan 0 curve invalid. Check your devicetree.cb.\n"); + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ + return; + } + + for (i = 0; i < IT5570_FAN_CNT; ++i) { + if (!is_curve_valid(config->fans[i].curve)) { + printk (BIOS_WARNING, "EC: Fan %d curve invalid. Using fan 0 curve.\n", i); + write_it5570_fan_curve(config->fans[0].curve, i); + } else { + write_it5570_fan_curve(config->fans[i].curve, i); + } + } + + /* Enable custom fan mode */ + acpigen_write_store_int_to_namestr(0x04, "FDAT"); + acpigen_write_store_int_to_namestr(0xD7, "FCMD"); + } + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ +} + +static const char *clevo_it5570_ec_acpi_name(const struct device *dev) +{ + return "EC0"; +} + +static struct device_operations ops = { + .init = clevo_it5570_ec_init, + .read_resources = clevo_it5570_ec_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = clevo_it5570_ec_fill_ssdt_generator, + .acpi_name = clevo_it5570_ec_acpi_name, +}; + +static struct pnp_info info[] = { + { NULL, 0, 0, 0, } +}; + +static void clevo_it5570_ec_enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(info), info); +} + +struct chip_operations ec_clevo_it5570_ops = { + CHIP_NAME("Clevo ITE IT5570 EC") + .enable_dev = clevo_it5570_ec_enable_dev, +}; diff --git a/src/ec/clevo/it5570/chip.h b/src/ec/clevo/it5570/chip.h new file mode 100644 index 0000000..af34b32 --- /dev/null +++ b/src/ec/clevo/it5570/chip.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EC_CLEVO_IT5570_CHIP_H +#define EC_CLEVO_IT5570_CHIP_H + +#include <acpi/acpi_device.h> + +#define IT5570_FAN_CURVE_LEN 0x4 /* Number of fan curve points */ +#define IT5570_FAN_CNT 0x3 /* Number of configurable fans */ + +enum ec_clevo_it5570_fan_mode { + FAN_MODE_AUTO = 0, + FAN_MODE_CUSTOM, +}; + +struct ec_clevo_it5570_fan_curve { + u8 temperature[IT5570_FAN_CURVE_LEN]; + u8 speed[IT5570_FAN_CURVE_LEN]; +}; + +struct ec_clevo_it5570_fan_config { + struct ec_clevo_it5570_fan_curve curve; +}; + +struct ec_clevo_it5570_config { + enum ec_clevo_it5570_fan_mode fan_mode; + struct ec_clevo_it5570_fan_config fans[IT5570_FAN_CNT]; +}; + +#endif /* EC_CLEVO_IT5570_CHIP_H */ diff --git a/src/ec/clevo/it5570/ec.c b/src/ec/clevo/it5570/ec.c new file mode 100644 index 0000000..d2e58f1 --- /dev/null +++ b/src/ec/clevo/it5570/ec.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> + +#include "ec.h" + +#define CLEVO_EC_CMD_ENABLE_ACPI_MODE 0x90 +#define CLEVO_EC_CMD_DISABLE_ACPI_MODE 0x91 + +void clevo_it5570_ec_smi_apmc(int apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(CLEVO_EC_CMD_ENABLE_ACPI_MODE); + send_ec_command(0x98); + ec_clr_bit(0xe8, 2); + break; + case APM_CNT_ACPI_DISABLE: + send_ec_command(CLEVO_EC_CMD_DISABLE_ACPI_MODE); + break; + default: + break; + } + +} diff --git a/src/ec/clevo/it5570/ec.h b/src/ec/clevo/it5570/ec.h new file mode 100644 index 0000000..be0927a --- /dev/null +++ b/src/ec/clevo/it5570/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void clevo_it5570_ec_smi_apmc(int apmc); -- To view, visit https://review.coreboot.org/c/coreboot/+/62495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c7d1d4f86d764bd10cfa3b0da23d1116281f3b Gerrit-Change-Number: 62495 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intelblocks/pep: Add display on/off notifications and handle TBT disp...
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62494 to review the following change. Change subject: intelblocks/pep: Add display on/off notifications and handle TBT displays ...................................................................... intelblocks/pep: Add display on/off notifications and handle TBT displays Add display on and off notifications which call mainboard hooks if present. This allows to handle some board specific functions in user absence or presence (whe ndisplay goes off from inactivity or on from activity). Additionally notify IOM to enable or disable TBT displays on S0ix exit and entry respectively. TEST=Use Display on/off notification on Clevo NV41 to tell EC about laptop inactivity. It is necessary to properly handle S0ix entry (stop the fans and start blinking the power led). Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62494/1 diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 8419a33..8ca823b 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -14,8 +14,11 @@ #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" #define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX" #define MAINBOARD_HOOK "\\_SB.MS0X" +#define MAINBOARD_DISPLAY_HOOK "\\_SB.MDSX" #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM" #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM" +#define THUNDERBOLT_DEVICE "\\_SB.PCI0.TXHC" +#define THUNDERBOLT_IOM_DPOF "\\_SB.PCI0.DPOF" #define LPI_STATES_ALL 0xff #define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0 #define PEPD_SCOPE "\\_SB.PCI0" @@ -125,6 +128,11 @@ acpigen_write_if_cond_ref_of(ENABLE_PM_BITS_HOOK); acpigen_emit_namestring(ENABLE_PM_BITS_HOOK); acpigen_write_if_end(); + + /* Handle Thunderbolt displays */ + acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE); + acpigen_write_store_int_to_namestr(1, THUNDERBOLT_IOM_DPOF); + acpigen_write_if_end(); } static void lpi_s0ix_exit(void *unused) @@ -145,14 +153,37 @@ acpigen_write_if_cond_ref_of(RESTORE_PM_BITS_HOOK); acpigen_emit_namestring(RESTORE_PM_BITS_HOOK); acpigen_write_if_end(); + + /* Handle Thunderbolt displays */ + acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE); + acpigen_write_store_int_to_namestr(0, THUNDERBOLT_IOM_DPOF); + acpigen_write_if_end(); +} + +static void lpi_display_on(void *unused) +{ + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK); + acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); +} + +static void lpi_display_off(void *unused) +{ + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK); + acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); } static void (*lpi_s0_helpers[])(void *) = { NULL, /* enumerate functions (autogenerated) */ lpi_get_constraints, /* get device constraints */ NULL, /* get crash dump device */ - NULL, /* display off notify */ - NULL, /* display on notify */ + lpi_display_off, /* display off notify */ + lpi_display_on, /* display on notify */ lpi_s0ix_entry, /* s0ix entry */ lpi_s0ix_exit, /* s0ix exit */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4 Gerrit-Change-Number: 62494 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Attention is currently required from: Michał Żygowski, Christian Walter. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62493 to review the following change. Change subject: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path ...................................................................... drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path Windows 11 expect the TPM to reside under \\_SB_.PCI0 in ACPI device hierarchy, otherwise the TPM is not detected. Hardcode the path to fix the issue TEST=Boot Windows 11 on Clevo NV41MZ and see the TPm is detected correctly Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 --- M src/drivers/pc80/tpm/tis.c 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62493/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 455bcf9..cf46f76 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -779,12 +779,8 @@ #if CONFIG(HAVE_ACPI_TABLES) static void lpc_tpm_fill_ssdt(const struct device *dev) { - const char *path = acpi_device_path(dev->bus->dev); - - if (!path) { - path = "\\_SB_.PCI0.LPCB"; - printk(BIOS_DEBUG, "Using default TPM ACPI path: '%s'\n", path); - } + /* Windows 11 requires the following path for TPM to be detected */ + const char *path = "\\_SB_.PCI0"; /* Device */ acpigen_write_scope(path); -- To view, visit https://review.coreboot.org/c/coreboot/+/62493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Gerrit-Change-Number: 62493 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Hide PMC and IOM devices
by Michał Kopeć (Code Review) 01 Mar '22

01 Mar '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62492 ) Change subject: soc/intel/tigerlake: Hide PMC and IOM devices ...................................................................... soc/intel/tigerlake: Hide PMC and IOM devices Windows complains on missing drivers for these ACPI devices. Hide them from OS as it doesn't influence the hardware operation. Linux can still probe the drivers correctly. TEST=Boot Windows 11 and see there are no devices with missing drivers. Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are still probed. Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572 --- M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/pmc.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/62492/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 1d58bfb..b349d54 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -336,6 +336,8 @@ Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) + /* Hide the device so that Windows will nto complain on missing driver */ + Name (_STA, 0xB) } /* diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 937943a..9ab28c2 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -106,6 +106,8 @@ acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); + /* Hide the device so that Windows will nto complain on missing driver */ + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). -- To view, visit https://review.coreboot.org/c/coreboot/+/62492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572 Gerrit-Change-Number: 62492 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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